Ahmad Sharkia

Orcid: 0000-0003-2260-7674

According to our database1, Ahmad Sharkia authored at least 7 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking.
IEEE J. Solid State Circuits, October, 2023

A Hierarchical Self-Interference Canceller for Full-Duplex LPWAN Applications Achieving 52-70-dB RF Cancellation.
IEEE J. Solid State Circuits, May, 2023

2019
A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-Gb/s -18.8 dBm Sensitivity 5.7 mW Fully-Integrated Optoelectronic Receiver With Avalanche Photodetector in 0.13- $\mu$ m CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Type-I Sub-Sampling PLL With a 100×100 µm<sup>2</sup> Footprint and -255-dB FOM.
IEEE J. Solid State Circuits, 2018

A 0.01mm<sup>2</sup> 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015
A high-performance, yet simple to design, digital-friendly type-I PLL.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015


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