Sudip Shekhar

Orcid: 0000-0003-0383-1929

According to our database1, Sudip Shekhar authored at least 74 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Enabling data-driven and bidirectional model development in Verilog-A for photonic devices.
CoRR, 2024

Dynamic Electro-Optic Analog Memory for Neuromorphic Photonic Computing.
CoRR, 2024

2023
A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking.
IEEE J. Solid State Circuits, October, 2023

A Hierarchical Self-Interference Canceller for Full-Duplex LPWAN Applications Achieving 52-70-dB RF Cancellation.
IEEE J. Solid State Circuits, May, 2023

Improving Linearity in CMOS Phase Interpolators.
IEEE J. Solid State Circuits, 2023

A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength.
IEEE J. Solid State Circuits, 2023

65 GOPS/neuron Photonic Tensor Core with Thin-film Lithium Niobate Photonics.
CoRR, 2023

Photon-pair generation from two silicon micro-rings using the recycled optical power from a contra-directional pump-reject filter.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2022
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20-28GHz LCVCO and a 51-62GHz Self-Mixing LCVCO.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Optimum Conditions for Efficient Second-Harmonic Power Generation in mm-Wave Harmonic Oscillators.
IEEE J. Solid State Circuits, 2022

A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Full-Duplex Wireless for (Joint-) Communication and Sensing.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2021

Monolithic Silicon Photonic Architecture for Training Deep Neural Networks with Direct Feedback Alignment.
CoRR, 2021

Scaling Up Silicon Photonic-based Accelerators: Challenges and Opportunities, and Roadmapping with Silicon Photonics 2.0.
CoRR, 2021

Prospects and applications of photonic neural networks.
CoRR, 2021

Neuromorphic Photonic Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

F6: Optical and Electrical Transceivers for 400GbE and Beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Stable Laser Without a Magneto-optic Isolator.
Proceedings of the European Conference on Optical Communication, 2021

A Case for Emerging Memories in DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
On the Design of Low-Power Hybrids for Full Duplex Simultaneous Bidirectional Signaling Links.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength.
IEEE J. Solid State Circuits, 2020

Injection Locking in Switching Power Amplifiers.
IEEE Access, 2020

A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A Supply-Noise-Insensitive Digitally-Controlled Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-Gb/s -18.8 dBm Sensitivity 5.7 mW Fully-Integrated Optoelectronic Receiver With Avalanche Photodetector in 0.13- $\mu$ m CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR.
IEEE J. Solid State Circuits, 2019

A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Type-I Sub-Sampling PLL With a 100×100 µm<sup>2</sup> Footprint and -255-dB FOM.
IEEE J. Solid State Circuits, 2018

A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

Compact Silicon Microring Modulator with Tunable Extinction Ratio and Wide FSR.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A 0.01mm<sup>2</sup> 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Digitally Controlled Analog Cancellation for Full Duplex Broadband Power Line Communications.
IEEE Trans. Commun., 2017

Automatic tuning and temperature stabilization of high-order silicon Vernier microring filters.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

A low-power temperature sensing system for implantable biomedical applications.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Analog interference cancellation for full-duplex broadband power line communications.
Proceedings of the IEEE International Symposium on Power Line Communications and its Applications, 2017

Session 2 - Wireline techniques for advanced modulation schemes.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
In-Band Full Duplex Broadband Power Line Communications.
IEEE Trans. Commun., 2016

On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise.
IEEE J. Solid State Circuits, 2016

Automatic wavelength tuning of series-coupled Vernier racetrack resonators on SOI.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Enhancing transmission efficiency of broadband PLC systems with In-Band Full Duplexing.
Proceedings of the International Symposium on Power Line Communications and its Applications, 2016

Silicon-photonic devices: Electronic control and stabilization.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR.
Proceedings of the Symposium on VLSI Circuits, 2015

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A high-performance, yet simple to design, digital-friendly type-I PLL.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
IEEE J. Solid State Circuits, 2014

A low-power DC-to-27-GHz transimpedance amplifier in 0.13-µm CMOS using inductive-peaking and current-reuse techniques.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.
IEEE J. Solid State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Design considerations for low-power receiver front-end in high-speed data links.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

U-shaped slow-wave transmission lines in 0.18μm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18/μm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Wideband CMOS Amplifier Design: Time-Domain Considerations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits.
IEEE J. Solid State Circuits, 2008

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
Bandwidth Extension Techniques for CMOS Amplifiers.
IEEE J. Solid State Circuits, 2006

A fully-differential CMOS Clapp VCO for IEEE 802.11a applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A delay generation technique for fast-locking frequency synthesizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A capacitor cross-coupled common-gate low-noise amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

G<sub>m</sub>-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

2004
Design considerations for anti-phase injected quadrature voltage controlled oscillators.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004


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