Alejandro F. González

According to our database, Alejandro F. González authored at least 10 papers between 1997 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

A spatio-temporal access method based on snapshots and events.

Gilberto A. Gutiérrez, Gonzalo Navarro, M. Andrea Rodríguez, Alejandro F. González, José Orellana

Proceedings of the 13th ACM International Workshop on Geographic Information Systems, 2005

2003

Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes.

Alejandro F. González, Pinaki Mazumder

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2001

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices.

Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder

IEEE J. Solid State Circuits, 2001

A 250-MHz, 32-bit quantum MOS correlator prototype.

Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González, Pinaki Mazumder

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Redundant arithmetic, algorithms and implementations.

Alejandro F. González, Pinaki Mazumder

Integr., 2000

Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.

Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

A prototyping technique for large-scale RTD-CMOS circuits.

Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices.

Alejandro F. González, Pinaki Mazumder

IEEE Trans. Computers, 1998

Circuit Design using Resonant Tunneling Diodes.

Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Compact Signed-Digit Adder Using Multiple-Valued Logic.

Alejandro F. González, Pinaki Mazumder

Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997