Mayukh Bhattacharya

According to our database1, Mayukh Bhattacharya authored at least 13 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Innovative practices on functional testing and fault simulation for FuSa.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2001
A physical design tool for built-in self-repairable RAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Modeling of Nonuniform Interconnects by Using Differential Quadrature Method.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
Convergence Issues in Resonant Tunneling Diode Circuit Simulation.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

A prototyping technique for large-scale RTD-CMOS circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A Physical Design Tool for Built-in Self-Repairable Static RAMs.
Proceedings of the 1999 Design, 1999

1998
Circuit Design using Resonant Tunneling Diodes.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998


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