Alexander Sudnitson

According to our database1, Alexander Sudnitson authored at least 28 papers between 2002 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
RAM-based mergers for data sort and frequent item computation.
Proceedings of the 40th International Convention on Information and Communication Technology, 2017

Reconfigurable systems in engineering education: Best practices and future trends.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

2016
Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems.
Int. J. Comput. Commun. Control, 2016

2015
Integration of high-level synthesis to the courses on reconfigurable digital systems.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

FPGA-based time and cost effective Hamming weight comparators for binary vectors.
Proceedings of the IEEE EUROCON 2015, 2015

Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
FPGA-based Accelerators for Parallel Data Sort.
Appl. Comput. Syst., 2014

Teaching FPGA-based systems.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

Design space exploration in multi-level computing systems.
Proceedings of the 15th International Conference on Computer Systems and Technologies, 2014

2013
Implementation of parallel operations over streams in extensible processing platforms.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Implementation of address-based data sorting on different FPGA platforms.
Proceedings of the East-West Design & Test Symposium, 2013

Address-based data processing over N-ary trees.
Proceedings of Eurocon 2013, 2013

Optimization of address-based data sorting unit with external memory support.
Proceedings of the Computer Systems and Technologies, 2013

2012
Performance evaluation for FPGA-based processing of tree-like structures.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Methodology and international collaboration in teaching reconfigurable systems.
Proceedings of the IEEE Global Engineering Education Conference, 2012

2011
Using SAT-Based Techniques in Low Power State Assignment.
J. Circuits Syst. Comput., 2011

Implementation in FPGA of Address-Based Data Sorting.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

High-performance hardware accelerators for sorting and managing priorities.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Recursion and hierarchy in digital design and prototyping: a case study.
Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

2010
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Application-specific hardware accelerator for implementing recursive sorting algorithms.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Advanced topics of FSM design using FPGA educational boards and web-based tools.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
FSM decomposition with application to FPGA synthesis.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2008
FPGA platform based digital design education.
Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2008

2004
Asynchronous e-learning resources for hardware design issues.
Proceedings of the 5th International Conference on Computer Systems and Technologies, 2004

2003
A decomposition procedure for register-transfer level power management.
Proceedings of the 4th International Conference on Computer Systems and Technologies: e-Learning, 2003

2002
Computational kernel extraction for synthesis of power-managed sequential components.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002


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