Artur Jutman

IEEE Instrum. Meas. Mag., 2017

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Marginal PCB assembly defect detection on DDR3/4 memory bus.

[BibT_eX]

[DOI]

Sergei Odintsov

Proceedings of the IEEE International Test Conference, 2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs.

[BibT_eX]

[DOI]

Konstantin Shibin

Proceedings of the 17th Latin-American Test Symposium, 2016

A suite of IEEE 1687 benchmark networks.

[BibT_eX]

[DOI]

Farrokh Ghani Zadegan

Riccardo Cantoro

Mehrdad Montazeri

Rene Krenz-Baath

Proceedings of the 2016 IEEE International Test Conference, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

On coverage of timing related faults at board level.

[BibT_eX]

[DOI]

Igor Aleksejev

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

No Fault Found: The root cause.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Virtual reconfigurable scan-chains on FPGAs for optimized board test.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

2014

Asynchronous Fault Detection in IEEE P1687 Instrument Network.

[BibT_eX]

[DOI]

Konstantin Shibin

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Design, Verification, and Application of IEEE 1687.

[BibT_eX]

[DOI]

Farrokh Ghani Zadegan

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

High Quality System Level Test and Diagnosis.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

Hans-Joachim Wunderlich

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management.

[BibT_eX]

[DOI]

Konstantin Shibin

IEEE Des. Test, 2013

On in-system programming of non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012

FPGA-based synthetic instrumentation for board test.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Embedded synthetic instruments for Board-Level testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Re-using chip level DFT at board level.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Erik Larsson

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Invited paper: System-wide fault management based on IEEE P1687 IJTAG.

[BibT_eX]

[DOI]

Igor Aleksejev

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

SoC and Board Modeling for Processor-Centric Board Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Structural fault collapsing by superposition of BDDs for test generation in digital circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Fault collapsing with linear complexity in digital circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Testing beyond the SoCs in a lego style.

[BibT_eX]

[DOI]

Anton Tsertov

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Parallel X-fault simulation with critical path tracing technique.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems.

[BibT_eX]

[DOI]

Heinz-Dietrich Wuttke

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Turning JTAG inside out for fast extended test access.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

Fast extended test access via JTAG and FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Structurally synthesized multiple input BDDs for simulation of digital circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2008

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Reseeding using compaction of pre-generated LFSR sub-sequences.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Calculation of LFSR Seed and Polynomial Pair for BIST Applications.

[BibT_eX]

[DOI]

Anton Tsertov

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Parallel fault backtracing for calculation of fault coverage.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Learning Digital Test and Diagnostics via Internet.

[BibT_eX]

[DOI]

Heinz-Dietrich Wuttke

Int. J. Online Eng., 2007

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

2006

DefSim: CMOS Defects on Chip for Research and Education.

[BibT_eX]

Proceedings of the 7th Latin American Test Workshop, 2006

Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs.

[BibT_eX]

Proceedings of the 7th Latin American Test Workshop, 2006

Off-Line Testing of Delay Faults in NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs.

[BibT_eX]

[DOI]

Proceedings of the Dependable Computing, 2005

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

At-speed on-chip diagnosis of board-level interconnect faults.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Asynchronous e-learning resources for hardware design issues.

[BibT_eX]

[DOI]

Alexander Sudnitson

Heinz-Dietrich Wuttke

Proceedings of the 5th International Conference on Computer Systems and Technologies, 2004

2002

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods.

[BibT_eX]

[DOI]

Jaan Raik

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Practical works for on-line teaching design and test of digital circuits.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Timing simulation of digital circuits with binary decision diagrams.

[BibT_eX]

[DOI]