Margus Kruus

Orcid: 0000-0003-3515-1290

According to our database1, Margus Kruus authored at least 16 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Reconfigurable systems in engineering education: Best practices and future trends.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

2015
Integration of high-level synthesis to the courses on reconfigurable digital systems.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

FPGA-based time and cost effective Hamming weight comparators for binary vectors.
Proceedings of the IEEE EUROCON 2015, 2015

2014
Hardware close programming for freshmen.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Teaching FPGA-based systems.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

2013
Address-based data processing over N-ary trees.
Proceedings of Eurocon 2013, 2013

2011
Recursion and hierarchy in digital design and prototyping: a case study.
Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

2010
Advanced topics of FSM design using FPGA educational boards and web-based tools.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
FSM decomposition with application to FPGA synthesis.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2008
FPGA platform based digital design education.
Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2008

2007
Learning Digital Test and Diagnostics via Internet.
Int. J. Online Eng., 2007

Graduate School in Information and Communication Technologies. Experiences at Tallinn University of Technology.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Hierarchical Identification of Untestable Faults in Sequential Circuits.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2003
A decomposition procedure for register-transfer level power management.
Proceedings of the 4th International Conference on Computer Systems and Technologies: e-Learning, 2003

2002
The Rational Unified Process with the "4+1" View Model of Software Architecture - a Way for Modeling Web Applications.
Proceedings of the Baltic Conference, 2002

2001
Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation.
VLSI Design, 2001


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