Dmitri Mihhailov

Orcid: 0000-0003-1167-2120

According to our database1, Dmitri Mihhailov authored at least 17 papers between 2008 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Architectural Exploration and Implementation of CERN LHC Trigger Algorithm With FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2025

2024
Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2022
HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study.
CoRR, 2022

2013
Implementation of address-based data sorting on different FPGA platforms.
Proceedings of the East-West Design & Test Symposium, 2013

Address-based data processing over N-ary trees.
Proceedings of Eurocon 2013, 2013

Optimization of address-based data sorting unit with external memory support.
Proceedings of the Computer Systems and Technologies, 2013

2012
Performance evaluation for FPGA-based processing of tree-like structures.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
EEG Analyzer prototype based on FPGA.
Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011

Implementation in FPGA of Address-Based Data Sorting.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

High-performance hardware accelerators for sorting and managing priorities.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Recursion and hierarchy in digital design and prototyping: a case study.
Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

2010
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Application-specific hardware accelerator for implementing recursive sorting algorithms.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Advanced topics of FSM design using FPGA educational boards and web-based tools.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
FSM decomposition with application to FPGA synthesis.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2008
FPGA platform based digital design education.
Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2008


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