Alexandre Verle

According to our database, Alexandre Verle authored at least 8 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2006

Circuit sizing method under delay constraint.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Speed Indicators for Circuit Optimization.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the Integrated Circuit and System Design, 2005

Circuit optimization based on speed indicators.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Low Power Oriented CMOS Circuit Optimization Protocol.

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the 2005 Design, 2005

2004

Performance Metric Based Optimization Protocol.

Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Delay bound based CMOS gate sizing technique.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

CMOS Gate Sizing under Delay Constraint.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003

Metric Definition for Circuit Speed Optimization.

Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003