Nadine Azémard

According to our database1, Nadine Azémard authored at least 54 papers between 1991 and 2019.

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Bibliography

2019
Energy Autonomous Wearable Sensors for Smart Healthcare: A Review.
CoRR, 2019

2018
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015.
J. Low Power Electronics, 2016

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices.
J. Low Power Electronics, 2016

Physical description and analysis of doped carbon nanotube interconnects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014.
J. Low Power Electronics, 2015

2014
Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013.
J. Low Power Electronics, 2014

2012
Delay-correlation-aware SSTA based on conditional moments.
Microelectronics Journal, 2012

Selected Articles from the VARI 2012 Workshop.
J. Low Power Electronics, 2012

Selected Articles from the VARI 2011 Workshop.
J. Low Power Electronics, 2012

Statistical timing characterization.
Proceedings of the 2012 International Symposium on System on Chip, 2012

2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectronics Journal, 2011

2010
On-Chip Process Variability Monitoring Flow.
J. Low Power Electronics, 2010

Selected Peer-Reviewed Articles from the VARI 2010 Workshop.
J. Low Power Electronics, 2010

2009
Timing margin evaluation with a simple statistical timing analysis flow.
J. Embedded Computing, 2009

Interpreting SSTA Results with Correlation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Product On-Chip Process Compensation for Low Power and Yield Enhancement.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
Editorial.
Integr., 2008

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

SSTA considering switching process induced correlations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Temperature- and Voltage-Aware Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Temperature and voltage aware timing analysis: application to voltage drops.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Logical effort model extension to propagation delay representation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
Integr., 2006

Statistical Characterization of Library Timing Performance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Timing analysis in presence of supply voltage and temperature variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Circuit sizing method under delay constraint.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Request-skip adders : CMOS standard cell data dependent adders.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Speed Indicators for Circuit Optimization.
Proceedings of the Integrated Circuit and System Design, 2005

Temperature Dependency in UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2005

Circuit optimization based on speed indicators.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Low Power Oriented CMOS Circuit Optimization Protocol.
Proceedings of the 2005 Design, 2005

2004
Performance Metric Based Optimization Protocol.
Proceedings of the Integrated Circuit and System Design, 2004

Physical Extension of the Logical Effort Model.
Proceedings of the Integrated Circuit and System Design, 2004

Temperature Dependence in Low Power CMOS UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2004

Design Optimization with Automated Cell Generation.
Proceedings of the Integrated Circuit and System Design, 2004

Delay bound based CMOS gate sizing technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
CMOS Gate Sizing under Delay Constraint.
Proceedings of the Integrated Circuit and System Design, 2003

Metric Definition for Circuit Speed Optimization.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Transition time modeling in deep submicron CMOS.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Structure Independent Representation of Output Transition Time for CMOS Library.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Gate speed improvement at minimal power dissipation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
POPS: A tool for delay/power performance optimization.
Journal of Systems Architecture, 2001

Delay bound determination for timing closure satisfaction.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Gate Sizing for Low Power Design.
Proceedings of the SOC Design Methodologies, 2001

Feasible Delay Bound Definition.
Proceedings of the SOC Design Methodologies, 2001

1996
Design and selection of buffers for minimum power-delay product.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Explicit evaluation of short circuit power dissipation for CMOS logic structures.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1993
Post-layout timing simulation of CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

1992
P.SIZE: a sizing aid for optimized designs.
Proceedings of the conference on European design automation, 1992

1991
Formal sizing rules of CMOS circuits.
Proceedings of the conference on European design automation, 1991


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