Nadine Azémard

According to our database, Nadine Azémard authored at least 59 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A mixed-signal oscillatory neural network for scalable analog computations in phase domain.

Corentin Delacour, Stefania Carapezzi, Gabriele Boschetto, Madeleine Abernot, Thierry Gil, Nadine Azémard, Aida Todri-Sanial

Neuromorph. Comput. Eng., September, 2023

2021

Oscillatory Neural Networks for Edge AI Computing.

Corentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Iterative Method for Performance Prediction Improvement of Integrated Circuits.

Gwenael Chaillou, Philippe Maurine, Jean-Marc Gallière, Nadine Azémard

Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2019

Energy Autonomous Wearable Sensors for Smart Healthcare: A Review.

Abhishek Singh Dahiya, Jerome Thireau, Jamila Boudaden, Swatchith Lal, Umair Gulzar, Yan Zhang, Thierry Gil, Nadine Azémard, Peter Ramm, Tim Kiessling, Cian O'Murchu, Fredrik Sebelius, Jonas Tilly, Colm Glynn, Shane Geary, Colm O'Dwyer, Kafil Razeeb, Alain Lacampagne, Benoît Charlot, Aida Todri-Sanial

CoRR, 2019

2018

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management.

Rida Kheirallah, Jean-Marc Gallière, Nadine Azémard, Gilles R. Ducharme

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017

Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic.

Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azémard, Aida Todri-Sanial

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016

Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015.

Ricardo Reis, Nadine Azémard

J. Low Power Electron., 2016

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices.

Rida Kheirallah, Gilles R. Ducharme, Nadine Azémard

J. Low Power Electron., 2016

Physical description and analysis of doped carbon nanotube interconnects.

Jie Liang, Liuyang Zhang, Nadine Azémard-Crestani, Pascal Nouet, Aida Todri-Sanial

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015

Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014.

Nadine Azémard, Eugeni García-Moreno

J. Low Power Electron., 2015

2014

Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013.

Nadine Azémard, Jörg Henkel

J. Low Power Electron., 2014

2012

Delay-correlation-aware SSTA based on conditional moments.

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme

Microelectron. J., 2012

Selected Articles from the VARI 2012 Workshop.

Nadine Azémard, Gilles Jacquemod

J. Low Power Electron., 2012

Selected Articles from the VARI 2011 Workshop.

Nadine Azémard, Marc Belleville

J. Low Power Electron., 2012

Statistical timing characterization.

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme

Proceedings of the 2012 International Symposium on System on Chip, 2012

2011

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.

Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard

Microelectron. J., 2011

2010

On-Chip Process Variability Monitoring Flow.

Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson

J. Low Power Electron., 2010

Selected Peer-Reviewed Articles from the VARI 2010 Workshop.

Nadine Azémard

J. Low Power Electron., 2010

2009

Timing margin evaluation with a simple statistical timing analysis flow.

V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine

J. Embed. Comput., 2009

Interpreting SSTA Results with Correlation.

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.

Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Product On-Chip Process Compensation for Low Power and Yield Enhancement.

Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

Editorial.

Nadine Azémard, Philippe Maurine, Johan Vounckx

Integr., 2008

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.

Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

SSTA considering switching process induced correlations.

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Temperature- and Voltage-Aware Timing Analysis.

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.

V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Temperature and voltage aware timing analysis: application to voltage drops.

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Logical effort model extension to propagation delay representation.

B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.

Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine

Integr., 2006

Statistical Characterization of Library Timing Performance.

V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Timing analysis in presence of supply voltage and temperature variations.

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine

Proceedings of the 2006 International Symposium on Physical Design, 2006

Circuit sizing method under delay constraint.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Request-skip adders : CMOS standard cell data dependent adders.

Robin Perrot, Nadine Azémard, Philippe Maurine

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Speed Indicators for Circuit Optimization.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the Integrated Circuit and System Design, 2005

Temperature Dependency in UDSM Process.

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine

Proceedings of the Integrated Circuit and System Design, 2005

Circuit optimization based on speed indicators.

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Low Power Oriented CMOS Circuit Optimization Protocol.

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the 2005 Design, 2005

2004

Performance Metric Based Optimization Protocol.

Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Physical Extension of the Logical Effort Model.

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Temperature Dependence in Low Power CMOS UDSM Process.

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Design Optimization with Automated Cell Generation.

A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Delay bound based CMOS gate sizing technique.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

CMOS Gate Sizing under Delay Constraint.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003

Metric Definition for Circuit Speed Optimization.

Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003

Continuous representation of the performance of a CMOS library.

B. Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the ESSCIRC 2003, 2003

2002

Transition time modeling in deep submicron CMOS.

Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Structure Independent Representation of Output Transition Time for CMOS Library.

Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Gate speed improvement at minimal power dissipation.

Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

POPS: A tool for delay/power performance optimization.

Nadine Azémard, Daniel Auvergne

J. Syst. Archit., 2001

Delay bound determination for timing closure satisfaction.

Nadine Azémard, M. Aline, Daniel Auvergne

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Gate Sizing for Low Power Design.

Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the SOC Design Methodologies, 2001

Feasible Delay Bound Definition.

Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne

Proceedings of the SOC Design Methodologies, 2001

1999

Delay-power performance analysis.

S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1996

Design and selection of buffers for minimum power-delay product.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Explicit evaluation of short circuit power dissipation for CMOS logic structures.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1993

Post-layout timing simulation of CMOS circuits.

Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

P.SIZE: a sizing aid for optimized designs.

Nadine Azémard, V. Bonzom, Daniel Auvergne

Proceedings of the conference on European design automation, 1992

1991

Formal sizing rules of CMOS circuits.

Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert

Proceedings of the conference on European design automation, 1991