Daniel Auvergne

According to our database, Daniel Auvergne authored at least 43 papers between 1985 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Logical effort model extension to propagation delay representation.

B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

Low Power Oriented CMOS Circuit Optimization Protocol.

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the 2005 Design, 2005

2004

Performance Metric Based Optimization Protocol.

Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Physical Extension of the Logical Effort Model.

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Temperature Dependence in Low Power CMOS UDSM Process.

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Design Optimization with Automated Cell Generation.

A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2004

Delay bound based CMOS gate sizing technique.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Design Techniques for EEPROMs Embedded in Portable Systems on Chips.

Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne

IEEE Des. Test Comput., 2003

CMOS Gate Sizing under Delay Constraint.

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003

Metric Definition for Circuit Speed Optimization.

Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne

Proceedings of the Integrated Circuit and System Design, 2003

Continuous representation of the performance of a CMOS library.

B. Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the ESSCIRC 2003, 2003

2002

Transition time modeling in deep submicron CMOS.

Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Crosstalk Measurement Technique for CMOS ICs.

Fabrice Picot, Philippe Coll, Daniel Auvergne

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Structure Independent Representation of Output Transition Time for CMOS Library.

Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.

Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications.

Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury

Proceedings of the 2002 Design, 2002

Gate speed improvement at minimal power dissipation.

Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

POPS: A tool for delay/power performance optimization.

Nadine Azémard, Daniel Auvergne

J. Syst. Archit., 2001

Output transition time modeling of CMOS structures.

Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Delay bound determination for timing closure satisfaction.

Nadine Azémard, M. Aline, Daniel Auvergne

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Gate Sizing for Low Power Design.

Philippe Maurine, Nadine Azémard, Daniel Auvergne

Proceedings of the SOC Design Methodologies, 2001

Feasible Delay Bound Definition.

Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne

Proceedings of the SOC Design Methodologies, 2001

2000

Second Generation Delay Model for Submicron CMOS Process.

Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne

Proceedings of the Integrated Circuit Design, 2000

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design.

Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne

Proceedings of the Integrated Circuit Design, 2000

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.

Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne

Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

1999

A comprehensive delay macro modeling for submicrometer CMOS logics.

Jean Michel Daga, Daniel Auvergne

IEEE J. Solid State Circuits, 1999

A Virtual CMOS Library Approach for East Layout Synthesis.

Fernando Moraes, Michel Robert, Daniel Auvergne

Proceedings of the VLSI: Systems on a Chip, 1999

RF Interface Design Using Mixed-Mode Methodology.

Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne

Proceedings of the VLSI: Systems on a Chip, 1999

Delay-power performance analysis.

S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A novel macromodel for power estimation in CMOS structures.

S. Turgis, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Temperature Effect on Delay for Low Voltage Applications.

Jean Michel Daga, E. Ottaviano, Daniel Auvergne

Proceedings of the 1998 Design, 1998

1997

Internal power modelling and minimization in CMOS inverters.

S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne

Proceedings of the European Design and Test Conference, 1997

1996

Delay propagation effect in transistor gates.

Denis Deschacht, Christophe Dabrin, Daniel Auvergne

IEEE J. Solid State Circuits, 1996

Design and selection of buffers for minimum power-delay product.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Explicit evaluation of short circuit power dissipation for CMOS logic structures.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Delay modelling improvement for low voltage applications.

Jean Michel Daga, Michel Robert, Daniel Auvergne

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Influence of Locig Block Layout Architecture on FPGA Performance.

Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne

Proceedings of the Field-Programmable Logic, 1994

1993

Post-layout timing simulation of CMOS circuits.

Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

P.SIZE: a sizing aid for optimized designs.

Nadine Azémard, V. Bonzom, Daniel Auvergne

Proceedings of the conference on European design automation, 1992

1991

TVA: A timing verifier with analytic temporal modelling.

D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne

Microprocessing and Microprogramming, 1991

Formal sizing rules of CMOS circuits.

Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert

Proceedings of the conference on European design automation, 1991

1990

Path runner: an accurate and fast timing analyser.

Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne

Proceedings of the European Design Automation Conference, 1990

1985

FSPICE: a tool for fault modelling in MOS circuits.

Michel Renovell, Gaston Cambon, Daniel Auvergne

Integr., 1985