Ali Dadashi

According to our database1, Ali Dadashi authored at least 13 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD).
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A Wide Band Fractional-N Synthesizer in 0.18um CMOS Process.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A New Very High-speed True 7-3 Compressor.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A 4.5 fJ/conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2016
Erratum: User Interface Problems of a Nationwide Inpatient Information System: A Heuristic Evaluation.
Appl. Clin. Inform., 2016

User Interface Problems of a Nationwide Inpatient Information System: A Heuristic Evaluation.
Appl. Clin. Inform., 2016

High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Novel high-speed dynamic differential ultra low voltage logic for supply-voltage below 300 mV.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2013
Modified telescopic amplifier with improved DC gain in 0.18 µm CMOS process.
Int. J. Circuit Theory Appl., 2013

2009
A new fully differential adaptive CMOS line driver suitable for ADSL applications.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009


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