Yngvar Berg

Orcid: 0000-0003-4519-995X

Affiliations:
  • University of Oslo, Norway


According to our database1, Yngvar Berg authored at least 110 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2019
A 4.5 fJ/conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Q-Loading of Colpitts-Based Mass-Sensing Oscillators in Resonator-based MEMS Airborne Particulate Matter (PM) Sensors.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Framework for Pupil-to-Student Transition, Learning Environment and Semester Start for First-Year Students.
Proceedings of the Digital Transformation for a Sustainable Society in the 21st Century, 2019

A Case-Study of Automated Feedback Assessment.
Proceedings of the IEEE Global Engineering Education Conference, 2019

Student Engagement by Employing Student Peer Reviews with Criteria-Based Assessment.
Proceedings of the IEEE Global Engineering Education Conference, 2019

2018
Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.
Sensors, 2018

A New Differential Oscillator with T-type Feedback.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

A Self-Actuated Front-End for Resonating Sensors.
Proceedings of the TENCON 2018, 2018

Studentaktivisering gjennom bruk av hverandrevurdering for førstesemesters studenter i Canvas LMS: en forsøksstudie.
Proceedings of the 31st Norsk Informatikkonferanse, 2018

A Discrete Implementation of a Semi-Floating Gate Amplifier for Resonating Sensor Front-End.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A bidirectional front-end for ultrasonic pulse-echo measurements.
Proceedings of the 15th IEEE International Conference on Networking, Sensing and Control, 2018

Formative feedback for learning. Case studies of automated feedback in undergraduate computer science education.
Proceedings of the Rethinking learning in the digital age: Making the Learning Sciences count, 2018

Structured peer review using a custom assessment program for electrical engineering students.
Proceedings of the 2018 IEEE Global Engineering Education Conference, 2018

2017
High-Speed Digital Domino Logic for Ultra-Low Supply Voltages.
Circuits Syst. Signal Process., 2017

Erfaringer fra strukturert peer review ved bruk av et egetutviklet sensureringsprogram.
Proceedings of the 30th Norsk Informatikkonferanse, 2017

A bidirectional front-end with bandwidth control for actuation and read-out of MEMS resonating sensors.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

A low power analog voltage similarity circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A control system for a low power bidirectional front-end for resonating sensors.
Proceedings of the 14th IEEE International Conference on Networking, Sensing and Control, 2017

A virtual Wheatstone bridge front-end for resistive sensors.
Proceedings of the 14th IEEE International Conference on Networking, Sensing and Control, 2017

An autozeroing inverter based front-end for resonating sensors.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016
Bidirectional front-end for piezoelectric resonator.
Proceedings of the 13th IEEE International Conference on Networking, Sensing, and Control, 2016

High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

A discrete implementation of a bidirectional circuit for actuation and read-out of resonating sensors.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A new self-sensing approach for actuation and readout of piezoelectric resonating sensor.
Proceedings of the 12th IEEE International Conference on Networking, Sensing and Control, 2015

Novel high-speed dynamic differential ultra low voltage logic for supply-voltage below 300 mV.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Low-voltage and high-speed CMOS circuit design with low-power mode.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
An ultra-low voltage tunable dual-Band Pass Filter.
Proceedings of the IEEE 11th International Multi-Conference on Systems, Signals & Devices, 2014

2011
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
Novel ultra low-voltage and high speed domino CMOS logic.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Static ultra-low-voltage high-speed CMOS logic and latches.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Ultra low voltage and high speed CMOS flip-flop using floating-gates.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

New SRAM design using body bias technique for ultra low power applications.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low Voltage Semi Floating-Gate Binary to Multiple-Value and Multiple-Value to Binary Converters.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Ultra low voltage static carry generate circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Novel ultra low voltage transconductance amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Reconfigurable pseudo floating-gate analog circuits.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Novel high speed and ultra low voltage CMOS flip-flops.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Clocked semi-floating-gate ultra low-voltage inverting current mirror.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Ultra low voltage semi-floating-gate transconductance amplifier based on binary inverters.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Novel high speed and ultra low voltage CMOS flip-flop.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Clocked semi-floating-gate ultra low-voltage current multiplier.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Clocked semi-floating-gate pseudo differential pair for low-voltage analog design.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Ultra low voltage and high speed CMOS carry generate circuits.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Ultra low-voltage switched current mirror.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Low voltage precharge CMOS logic.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
Real-Time Reconfigurable Subthreshold CMOS Perceptron.
IEEE Trans. Neural Networks, 2008

Ultra Low Voltage High Speed Differential CMOS Inverter.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

High Speed Ultra Low Voltage CMOS inverter.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Clocked semi-floating-gate ultra low-voltage current mirror.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Ultra low voltage and, nor and XOR CMOS gates.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

High speed and ultra low voltage CMOS latch.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Bi-directional Current-Starved Pseudo Floating-Gate differentiator / integrator.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Cascade of Current-Starved Pseudo Floating-Gate inverters.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low Voltage Design against Power Analysis Attacks.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Proposal for a Bidirectional Gate Using Pseudo Floating-Gate.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Fault Tolerant CMOS Logic Using Ternary Gates.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Band Pass Pseudo Floating-Gate Amplifier.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Pseudo Floating-Gate Inverter with Feedback Control.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Switched pseudo floating-gate reconfigurable linear threshold elements.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel ternary more, less and equality circuit using recharged semi-floating gate devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Ultra low voltage CMOS gates.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Multiple Valued Counter.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Self-refreshing Multiple Valued Memory.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004
A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Basic Multiple-Valued Functions Using Recharge CMOS Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Erratum to "real-time reconfigurable linear threshold elements implemented in floating-gate CMOS".
IEEE Trans. Neural Networks, 2003

Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS.
IEEE Trans. Neural Networks, 2003

UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3".
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

A low voltage second order biquad using pseudo floating-gate transistors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Tunable floating-gate low-voltage transconductor.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency tripler.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Delta-sigma modulation in single neurons.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low-voltage sinc<sup>2</sup> decimator implemented by a new circuit technique using floating-gate MOS transistors.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel floating-gate multiple-valued CMOS full-adder.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A novel floating-gate multiple-valued signal to binary signal converter.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Floating-gate CMOS differential analog inverter for ultra low-voltage applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Extreme low-voltage floating-gate CMOS transconductance amplifier.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel low-voltage floating-gate CMOS transconductance amplifier with sinh (tanh) shaped output current.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A 0.3 V floating-gate differential amplifier input stage with tunable gain.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Novel reconfigurable two-MOSFET UV-programmable floating-gate circuits for CARRY, NAND, NOR or INVERT functions.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Tunable ultralow voltage transconductance amplifier and GmC filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Neuromorphic cochlea implants.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Ultralow-voltage floating-gate analog multiplier with tunable linearity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Ultra low-voltage floating-gate transconductance amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Ultra low-voltage floating-gate transconductance amplifier with tunable gain and linearity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Area efficient circuit tuning with floating-gate techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Tunable current mirrors for ultra low voltage.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Ultra low voltage current multiplier/divider.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Ultra low voltage transconductance amplifier.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
FLOGIC-Floating-gate logic for low-power operation.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
Scalable Mean Rate Signal Encoding Analog Neural Network.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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