Khayrollah Hadidi

According to our database1, Khayrollah Hadidi authored at least 102 papers between 1994 and 2022.

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Bibliography

2022
A new background continuous-time offset cancelation and gain calibration strategy for open-loop residue amplifiers in high-speed and high-resolution ADC's.
Int. J. Circuit Theory Appl., December, 2022

2021
A 12-Gb/s serial link transceiver using dual-mode pulse amplitude modulation scheme in a 0.18-μm CMOS process.
Int. J. Circuit Theory Appl., 2021

A New Low Power Mixed-Signal Digital Voltage Mode CMOS Fuzzy Logic Controller.
Circuits Syst. Signal Process., 2021

2020
A new mixed-signal CMOS fuzzy logic controller in current mode.
J. Intell. Fuzzy Syst., 2020

Design Analysis and Evaluation of a W-Element Model for a Twisted-Pair Cable.
IEEE Access, 2020

A New Adaptive Prioritization and Fail-Over Mechanism for Ring Network Adapter.
IEEE Access, 2020

2019
A fuzzy Anti-lock braking system (ABS) controller using CMOS circuits.
Microprocess. Microsystems, 2019

2018
A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs.
Integr., 2018

Low-jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers.
IET Circuits Devices Syst., 2018

A low-power, fully programmable membership function generator using both transconductance and current modes.
Fuzzy Sets Syst., 2018

2016
High-Speed General Purpose Genetic Algorithm Processor.
IEEE Trans. Cybern., 2016

A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An 8B/10B encoder with 2GHz operating frequency.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs.
Proceedings of the 2016 MIXDES, 2016

A new ultra high speed 5-2 compressor with a new structure.
Proceedings of the 2016 MIXDES, 2016

A new adaptive PLL to reduce the lock time in 0.18µm technology.
Proceedings of the 2016 MIXDES, 2016

2015
Power and area reduction in CMOS analog fuzzy logic controllers by using a new inference engine structure.
J. Intell. Fuzzy Syst., 2015

CMOS implementation of a current-mode fully programmable interval type-2 fuzzifier.
J. Intell. Fuzzy Syst., 2015

Analysis and Design of a Precise Voltage Buffer.
J. Circuits Syst. Comput., 2015

A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump.
J. Circuits Syst. Comput., 2015

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs.
J. Circuits Syst. Comput., 2015

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process.
J. Circuits Syst. Comput., 2015

High speed, open loop residue amplifier with linearity improvement.
IET Circuits Devices Syst., 2015

High gain two-stage amplifier with positive capacitive feedback compensation.
IET Circuits Devices Syst., 2015

CMOS fuzzy logic controller supporting fractional polynomial membership functions.
Fuzzy Sets Syst., 2015

Fast and accurate fractional frequency synthesizer in 0.18μm technology.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

A 6-bit 800MS/s flash ADC in 0.35μm CMOS.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

A new ultra high speed 7-2 compressor with a new structure.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

An ultra high speed booth encoder structure for fast arithmetic operations.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
A circuit implementation of an ultra high speed, low power analog fully programmable MFG.
J. Intell. Fuzzy Syst., 2014

Design of current-mode modular programmable analog CMOS FLC.
J. Intell. Fuzzy Syst., 2014

100 MS/S, 10-Bit ADC using Pipelined Successive Approximation.
J. Circuits Syst. Comput., 2014

A Fast and Low Settling error continuous-Time Common-mode feedback Circuit Based on differential difference amplifier.
J. Circuits Syst. Comput., 2014

A Low Power 13-Bit 50MS/S Recirculating Pipeline Analog to Digital Converter.
J. Circuits Syst. Comput., 2014

A Wide-Range Programmable Pulse Width controller.
J. Circuits Syst. Comput., 2014

A Fully Programmable Analog CMOS Rational-Powered Membership Function Generator with Continuously Adjustable High Precision Parameters.
Circuits Syst. Signal Process., 2014

A novel high-speed 4-bit carry generator with a new structure for arithmetic operations.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A novel fast glitchless 7-3 counter with a new structure.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A novel mixed-signal digital CMOS fuzzy logic controller in current mode.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A novel method in fractional synthesizers for a drastic decrease in lock time.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A novel mixed-signal digital voltage mode CMOS fuzzy logic controller in 0.18μm technology.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A novel fast glitchless 4-2 compressor with a new structure.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

A highly accurate fuzzifier in current mode with low power consumption.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

2013
CMOS implementation of a new high speed 5-2 compressor for parallel accumulations.
IEICE Electron. Express, 2013

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

A circuit implementation of an ultra high speed, low power analog fully programmable MFG.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

The sundial based sun-tracking system with AVR microcontroller.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

A high speed and fully tunable MFG with new programmable CMOS OTA and new MIN circuit.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations.
IEICE Trans. Electron., 2012

Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations.
IEICE Trans. Electron., 2012

CMOS implementation of a fast 4-2 compressor for parallel accumulations.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Input dependent clock jitter in high speed and high resolution ADCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel quantization algorithm suitable for high-speed analog-to-digital converters.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Digitally-controlled Gm-C bandpass filter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A 500 MS/s 600 µW 300 µm<sup>2</sup> Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process.
IEICE Trans. Electron., 2011

High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of a programmable analog CMOS rational-powered membership function generator in current mode approach.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A highly accurate fully programmable fuzzifier in current mode approach.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fast and flexible genetic algorithm processor.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A 1GS/s low-power low-kickback noise comparator in CMOS process.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
CMOS model selection for simulation using fuzzy inference system.
IEICE Electron. Express, 2010

Current-mode analog CMOS Fuzzy Logic Controller.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A highly linear open-loop high-speed CMOS sample-and-hold.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A new linear readout circuit for a CMOS image sensor.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A CMOS 3.2 GB/s serial link transceiver, using PWM and PAM scheme.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A new fully differential adaptive CMOS line driver suitable for ADSL applications.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Optimization of rational-powered membership functions using extended Kalman filter.
Fuzzy Sets Syst., 2008

2007
High Speed High Precision voltage-Mode Max and Min Circuits.
J. Circuits Syst. Comput., 2007

A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions.
IEICE Trans. Electron., 2007

Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Amplification.
IEICE Trans. Electron., 2007

Design of A New CMOS Controllable Mixed-Signal Current Mode Fuzzy Logic Controller (FLC) Chip.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A New ANFIS Based Learning Algorithm for CMOS Neuro-Fuzzy Controllers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

High Speed, Low Power Four-Quadrant CMOS Current-Mode Multiplier.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Open Loop Phase Shifter and Frequency Synthesizer.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
A High Speed and Compact Mixed-Signal CMOS Fuzzifier.
J. Circuits Syst. Comput., 2006

Modified CMOS Op-Amp with Improved Gain and Bandwidth.
IEICE Trans. Electron., 2006

Design of Analog Current-Mode Loser-Take-All Circuit.
IEICE Trans. Electron., 2006

A 1.5-V, Constant-Gm, Rail-to-Rail Input Stage Operational Amplifier.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A New Method for Offset Cancellation in High-Resolution High-Speed Comparators.
IEICE Trans. Electron., 2005

A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Low-Power, Small-Size 10-Bit Successive-Approximation ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Fuzzy level control of a tank with optimum valve movement.
Fuzzy Sets Syst., 2005

2003
A CMOS 310MHz, 20dB Variable Gain Amplifier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Design of a CMOS image sensor with pixel-level ADC in 0.35µm process.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A highly linear fully differential low power CMOS line driver.
Proceedings of the ESSCIRC 2003, 2003

2002
Design of an analog CMOS fuzzy logic controller chip.
Fuzzy Sets Syst., 2002

1998
A novel design technique for input differential pairs in single-ended operational amplifiers.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A novel highly linear CMOS buffer.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A 300 MHz 18 dB variable gain amplifier.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A highly linear second-order stage for 500-MHz third-order and fifth-order filters.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

An open-loop full CMOS 103 MHz -61 dB THD S/H circuit.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1996
Microprocessor based closed-loop speed control system for DC motor using power MOSFET.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A highly linear cascode-driver CMOS source-follower buffer.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994
A Novel Input Differential Pair for Improved Linearity Buffer and S/H Amplifier Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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