Morteza Mousazadeh

According to our database, Morteza Mousazadeh authored at least 20 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2022

Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection.

Seyed Kian Mousavikia, Erfan Gholizadehazari, Morteza Mousazadeh, Siddika Berna Örs Yalçin

IEEE Access, 2022

2021

A New True Random Number Generator Based on Differential Variable Ring Oscillator Robust Against PVT Variation.

Niloofar Khayyat Salighehdar, Morteza Mousazadeh, Abdolah Khoei

J. Circuits Syst. Comput., 2021

A new high speed and low power decoder/encoder for Radix-4 Booth multiplier.

Mir Majid Ghasemi, Amir Fathi, Morteza Mousazadeh, Abdollah Khoei

Int. J. Circuit Theory Appl., 2021

2020

A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure.

Alireza Abolhasani, Morteza Mousazadeh, Abdollah Khoei

Microelectron. J., 2020

Fast-locking PLL based on a novel PFD-CP structure and reconfigurable loop filter.

Alireza Abolhasani, Morteza Mousazadeh, Abdollah Khoei

IET Circuits Devices Syst., 2020

2019

Generalized Method of Analog Circuit Characteristic Function Analysis.

Amir Fathi, Abdollah Khoei, Morteza Mousazadeh

IEEE Trans. Circuits Syst. II Express Briefs, 2019

High-speed, low power, and dead zone improved phase frequency detector.

Amir Fathi, Morteza Mousazadeh, Abdollah Khoei

IET Circuits Devices Syst., 2019

A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD).

Zaher Kakehbra, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A Wide Band Fractional-N Synthesizer in 0.18um CMOS Process.

Ebrahim Hosseini, Morteza Mousazadeh, Ali Dadashi

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A New Very High-speed True 7-3 Compressor.

Sara Ghafari, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method.

Sara Ghafari, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2018

High-Speed 32*32 bit Multiplier in 0.18um CMOS Process.

Ebrahim Hosseini, Morteza Mousazadeh, Abdollah Amini

Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2016

An 8B/10B encoder with 2GHz operating frequency.

Hamed Ashrafi, Morteza Mousazadeh, Khayrollah Hadidi

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2013

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations.

Mohammad Tohidi, Morteza Mousazadeh, Saeed Akbari, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

A circuit implementation of an ultra high speed, low power analog fully programmable MFG.

Mohammad Tohidi, Alireza Abolhasani, Morteza Mousazadeh, Abdollah Khoei, Khayrollah Hadidi

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

The sundial based sun-tracking system with AVR microcontroller.

Mostafa Amirpour, Morteza Mousazadeh, Mohammad Tohidi, Khayrollah Hadidi

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

A high speed and fully tunable MFG with new programmable CMOS OTA and new MIN circuit.

Alireza Abolhasani, Mohammad Tohidi, Morteza Mousazadeh, Abdollah Khoei, Khayrollah Hadidi

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2011

A 500 MS/s 600 µW 300 µm² Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process.

Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei

IEICE Trans. Electron., 2011

2010

A highly linear open-loop high-speed CMOS sample-and-hold.

Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection.

Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010