Omid Mirmotahari

According to our database1, Omid Mirmotahari authored at least 44 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 4.5 fJ/conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Framework for Pupil-to-Student Transition, Learning Environment and Semester Start for First-Year Students.
Proceedings of the Digital Transformation for a Sustainable Society in the 21st Century, 2019

A Case-Study of Automated Feedback Assessment.
Proceedings of the IEEE Global Engineering Education Conference, 2019

Student Engagement by Employing Student Peer Reviews with Criteria-Based Assessment.
Proceedings of the IEEE Global Engineering Education Conference, 2019

2018
En eksempel-studie av automatisk tilbakemelding for programmeringsfag i høyere utdanning.
Proceedings of the 31st Norsk Informatikkonferanse, 2018

Studentaktivisering gjennom bruk av hverandrevurdering for førstesemesters studenter i Canvas LMS: en forsøksstudie.
Proceedings of the 31st Norsk Informatikkonferanse, 2018

Structured peer review using a custom assessment program for electrical engineering students.
Proceedings of the 2018 IEEE Global Engineering Education Conference, 2018

2017
High-Speed Digital Domino Logic for Ultra-Low Supply Voltages.
Circuits Syst. Signal Process., 2017

Erfaringer fra strukturert peer review ved bruk av et egetutviklet sensureringsprogram.
Proceedings of the 30th Norsk Informatikkonferanse, 2017

A control system for a low power bidirectional front-end for resonating sensors.
Proceedings of the 14th IEEE International Conference on Networking, Sensing and Control, 2017

2016
Bidirectional front-end for piezoelectric resonator.
Proceedings of the 13th IEEE International Conference on Networking, Sensing, and Control, 2016

High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

A discrete implementation of a bidirectional circuit for actuation and read-out of resonating sensors.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Novel high-speed dynamic differential ultra low voltage logic for supply-voltage below 300 mV.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Low-voltage and high-speed CMOS circuit design with low-power mode.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2011
Fully parallel comparator for the moduli set {2<sup>n</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1}.
IEICE Electron. Express, 2011

2009
Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Clocked semi-floating-gate ultra low-voltage inverting current mirror.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Pareto Optimal Based Evolutionary Approach for Solving Multi-Objective Facility Layout Problem.
Proceedings of the Neural Information Processing, 16th International Conference, 2009

Clocked semi-floating-gate ultra low-voltage current multiplier.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Clocked semi-floating-gate pseudo differential pair for low-voltage analog design.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Ultra low voltage and high speed CMOS carry generate circuits.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Ultra low-voltage switched current mirror.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Low voltage precharge CMOS logic.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
Ultra Low Voltage High Speed Differential CMOS Inverter.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

High Speed Ultra Low Voltage CMOS inverter.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Clocked semi-floating-gate ultra low-voltage current mirror.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Ultra low voltage and, nor and XOR CMOS gates.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

High speed and ultra low voltage CMOS latch.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Bi-directional Current-Starved Pseudo Floating-Gate differentiator / integrator.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low Voltage Design against Power Analysis Attacks.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Proposal for a Bidirectional Gate Using Pseudo Floating-Gate.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Band Pass Pseudo Floating-Gate Amplifier.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Pseudo Floating-Gate Inverter with Feedback Control.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Ultra low voltage CMOS gates.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Basic Multiple-Valued Functions Using Recharge CMOS Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003
Difficulties learning computer architecture.
Proceedings of the 8th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2003

A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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