Ali Shahabi

Orcid: 0000-0002-6259-0179

According to our database1, Ali Shahabi authored at least 10 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
An event-driven simulation-optimisation approach to improve the resiliency of operation in a double-track urban rail line.
J. Simulation, 2022

2021
Designing a resilient skip-stop schedule in rapid rail transit using a simulation-based optimization methodology.
Oper. Res., 2021

2020
Experimental Validation of CT-Snubber for Multichip SiC MOSFET Power Module.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2014
Configurable Systolic Matrix Multiplication.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2012
A novel graceful degradable routing algorithm for 3D on-chip networks.
Proceedings of the 2012 Interconnection Network Architecture, 2012

2010
A partitioning approach to improve reconfigurable neuron-inspired online BIST.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A reconfigurable online BIST for combinational hardware using digital neural networks.
Proceedings of the 15th European Test Symposium, 2010

2007
Degradable mesh-based on-chip networks using programmable routing tables.
IEICE Electron. Express, 2007

High Level Synthesis of Degradable ASICs Using Virtual Binding.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Programmable Routing Tables for Degradable Torus-Based Networks on Chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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