Saeed Safari
Orcid: 0000-0001-6940-591X
According to our database1,
Saeed Safari
authored at least 84 papers
between 2003 and 2024.
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Bibliography
2024
Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems.
IEEE Access, 2024
2023
A Hardware-Friendly Real-Time Implementation of the Auditory Attention Based on a Novel Spiking Winner-Take-All Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2022
Compression of Deep Neural Networks based on quantized tensor decomposition to implement on reconfigurable hardware platforms.
Neural Networks, 2022
Adjoint recurrent neural network technique for nonlinear electronic component modeling.
Int. J. Circuit Theory Appl., 2022
2021
Modeling of single/multiple-bit upset effects on logic circuits applying Recurrent Neural Network.
Microelectron. J., 2021
Recurrent neural networks models for analyzing single and multiple transient faults in combinational circuits.
Microelectron. J., 2021
A Novel Approximate Hamming Weight Computing for Spiking Neural Networks: an FPGA Friendly Architecture.
CoRR, 2021
2020
EREER: Energy-aware register file and execution unit using exploiting redundancy in GPGPUs.
Microprocess. Microsystems, 2020
A digital hardware implementation of spiking neural networks with binary FORCE training.
Neurocomputing, 2020
A reconfigurable real-time neuromorphic hardware for spiking winner-take-all network.
Int. J. Circuit Theory Appl., 2020
2019
CMV: Clustered Majority Voting Reliability-Aware Task Scheduling for Multicore Real-Time Systems.
IEEE Trans. Reliab., 2019
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2019
Dynamic behavioral modeling of nonlinear circuits using a novel recurrent neural network technique.
Int. J. Circuit Theory Appl., 2019
Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks.
J. Electron. Test., 2019
A memory-efficient canonical data structure for decimal floating point arithmetic systems modeling and verification.
Turkish J. Electr. Eng. Comput. Sci., 2019
2018
A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC Architectures.
ACM Trans. Embed. Comput. Syst., 2018
Storage capacity for EDF-ASAP algorithm in energy-harvesting systems with periodic implicit deadline hard real-time tasks.
J. Syst. Archit., 2018
LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018
2017
LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions.
ACM Trans. Design Autom. Electr. Syst., 2016
Reliability aware throughput management of chip multi-processor architecture via thread migration.
J. Supercomput., 2016
An efficient temperature dependent hot carrier injection reliability simulation flow.
Microelectron. Reliab., 2016
PVTA-aware approximate custom instruction extension technique: A cross-layer approach.
Microelectron. Reliab., 2016
Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor.
Microprocess. Microsystems, 2016
Statistical analysis of asynchronous pipelines in presence of process variation using formal models.
Integr., 2016
Fast and accurate FPGA-based framework for processor architecture vulnerability analysis.
Integr., 2016
Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs.
ACM Trans. Embed. Comput. Syst., 2015
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation.
IET Comput. Digit. Tech., 2015
A cross-layer approach to online adaptive reliability prediction of transient faults.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014
Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors.
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Microprocess. Microsystems, 2013
Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture.
J. Real Time Image Process., 2013
Performance evaluation of normaly-off SiC JFET in matrix converter without antiparrallel diodes.
Proceedings of the IECON 2013, 2013
Capturing and mitigating the NBTI effect during the design flow for extensible processors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
DEED: Dynamic energy efficient distributed cluster forming algorithm for Wireless Sensors Network.
Proceedings of the 6th International Symposium on Telecommunications, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
FPGA Implementation of Hodgkin-Huxley Neuron Model.
Proceedings of the IJCCI 2012 - Proceedings of the 4th International Joint Conference on Computational Intelligence, Barcelona, Spain, 5, 2012
Proceedings of the Neural Information Processing - 19th International Conference, 2012
An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
An architecture-level approach for mitigating the impact of process variations on extensible processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Securing Embedded Processors against Power Analysis Based Side Channel Attacks Using Reconfigurable Architecture.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011
2010
Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization.
Eng. Appl. Artif. Intell., 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the Advances in Visual Computing - 6th International Symposium, 2010
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
2009
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Real-Time Parallel Implementation of SSD Stereo Vision Algorithm on CSX SIMD Architecture.
Proceedings of the Advances in Visual Computing, 5th International Symposium, 2009
A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages.
Proceedings of the IEEE International Conference on Acoustics, 2009
2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
IEICE Electron. Express, 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007
2006
Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003