Nima Honarmand

Orcid: 0000-0001-8634-1241

According to our database1, Nima Honarmand authored at least 19 papers between 2006 and 2019.

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Bibliography

2019
Massively Parallel Server Processors.
IEEE Comput. Archit. Lett., 2019

Time Does Not Heal All Wounds: A Longitudinal Analysis of Security-Mechanism Support in Mobile Browsers.
Proceedings of the 26th Annual Network and Distributed System Security Symposium, 2019

2018
Taming the Killer Microsecond.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Record-Replay Architecture as a General Security Framework.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Hindsight: Understanding the Evolution of UI Vulnerabilities in Mobile Browsers.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2015
Asymmetric Memory Fences: Optimizing Both Performance and Implementability.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Record and deterministic replay of parallel programs on multiprocessors
PhD thesis, 2014

Replay debugging: Leveraging record and replay for program debugging.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

RelaxReplay: record and replay for relaxed-consistency multiprocessors.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Cyrus: unintrusive application-level record-replay for replay parallelism.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2011
Safe nondeterminism in a deterministic-by-default parallel language.
Proceedings of the 38th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2011

DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2007
Degradable mesh-based on-chip networks using programmable routing tables.
IEICE Electron. Express, 2007

High Level Synthesis of Degradable ASICs Using Virtual Binding.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Programmable Routing Tables for Degradable Torus-Based Networks on Chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Power efficient sequential multiplication using pre-computation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low Power Combinational Multipliers using Data-driven Signal Gating.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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