Hasan Sohofi

According to our database1, Hasan Sohofi authored at least 9 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2015
System-level assertions: approach for electronic system-level verification.
IET Comput. Digit. Tech., 2015

Physical design aware system level synthesis of hardware.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2014
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.
Microprocess. Microsystems, 2014

Assertion-based verification for system-level designs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2010
A partitioning approach to improve reconfigurable neuron-inspired online BIST.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A reconfigurable online BIST for combinational hardware using digital neural networks.
Proceedings of the 15th European Test Symposium, 2010

2007
Degradable mesh-based on-chip networks using programmable routing tables.
IEICE Electron. Express, 2007

High Level Synthesis of Degradable ASICs Using Virtual Binding.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.
Proceedings of the Forum on specification and Design Languages, 2007


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