Alireza Hodjat

According to our database1, Alireza Hodjat authored at least 18 papers between 2003 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor.
Integr., 2007

2006
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.
IEEE Trans. Computers, 2006

AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.
IEEE J. Solid State Circuits, 2006

Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Security for Ambient Intelligent Systems.
Proceedings of the Ambient Intelligence, 2005

2004
High-Throughput Programmable Cryptocoprocessor.
IEEE Micro, 2004

Architectural Design Features of a Programmable High Throughput AES Coprocessor.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Embedded Software Integration for Coarse-Grain Reconfigurable Systems.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Testing ThumbPod: Softcore bugs are hard to find.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003


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