Bo-Cheng Lai

According to our database1, Bo-Cheng Lai authored at least 53 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Online presence:

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Bibliography

2020
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Novel Smart Assistance System for Blood Vessel Approaching: A Technical Report Based on Oximetry.
Sensors, 2020

Selective bypassing and mapping for heterogeneous applications on GPGPUs.
J. Parallel Distributed Comput., 2020

Dataflow and microarchitecture co-optimisation for sparse CNN on distributed processing element accelerator.
IET Circuits Devices Syst., 2020

A Two-Directional BigData Sorting Architecture on FPGAs.
IEEE Comput. Archit. Lett., 2020

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Efficient Write Scheme for Algorithm-Based Multi-Ported Memory.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2018
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning.
J. Parallel Distributed Comput., 2018

Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Efficient Designs of Multiported Memory on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Hadoop-based Principle Component Analysis on embedded heterogeneous platform.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016
Unified Designs for High Performance LDPC Decoding on GPGPU.
IEEE Trans. Computers, 2016

A Quantitative Method to Data Reuse Patterns of SIMT Applications.
IEEE Comput. Archit. Lett., 2016

Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPU.
Proceedings of the 10th International Conference on Complex, 2016

2015
A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2015

A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs.
IEEE Trans. Computers, 2015

Self adaptable multithreaded object detection on embedded multicore systems.
J. Parallel Distributed Comput., 2015

Power-Efficient Instancy Aware DRAM Scheduling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

BRAM efficient multi-ported memory on FPGA.
Proceedings of the VLSI Design, Automation and Test, 2015

Design of Application Specific Throughput Processor for Matrix Operations.
Proceedings of the 18th International Conference on Network-Based Information Systems, 2015

Computation and Communication Aware task graph Scheduling on multi-GPU systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2014

Reducing Contention in Shared Last-Level Cache for Throughput Processors.
ACM Trans. Design Autom. Electr. Syst., 2014

Automatic Data Layout Transformation for Heterogeneous Many-Core Systems.
Proceedings of the Network and Parallel Computing, 2014

A Cache Aware Multithreading Decision Scheme on GPGPUs.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

A learning-on-cloud power management policy for smart devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
A distributed thread scheduler for dynamic multithreading on throughput processors.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Memory capacity aware non-blocking data transfer on GPGPU.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

A Locality-Aware Dynamic Thread Scheduler for GPGPUs.
Proceedings of the International Conference on Parallel and Distributed Computing, 2013

Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A highly parallel design of image surface layout recovering on GPGPU.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Reduce Data Coherence Cost with an Area Efficient Double Layer Counting Bloom Filter.
Proceedings of the Fifth International Symposium on Parallel Architectures, 2012

Thread affinity mapping for irregular data access on shared Cache GPGPU.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A highly parallel design for irregular LDPC decoding on GPGPUs.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
Classifier Grouping to Enhance Data Locality for a Multi-threaded Object Detection Algorithm.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

2010
Unleash the parallelism of 3DIC partitioning on GPGPU.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2008
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.
IEEE Trans. Computers, 2008

2006
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005

Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.
Proceedings of the 42nd Design Automation Conference, 2005

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Security for Ambient Intelligent Systems.
Proceedings of the Ambient Intelligence, 2005

2004
Reducing radio energy consumption of key management protocols for wireless sensor networks.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Energy-Memory-Security Tradeoffs in Distributed Sensor Networks.
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks: Third International Conference, 2004

2003
Testing ThumbPod: Softcore bugs are hard to find.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003

2002
A Security Protocol for Biometric Smart Cards.
Proceedings of the Fifth Smart Card Research and Advanced Application Conference, 2002


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