Amer Samarah

According to our database1, Amer Samarah authored at least 7 papers between 2006 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2015
Cycle-slipping pull-in range of bang-bang PLLs.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC.
IEEE J. Solid State Circuits, 2013

2012
A dead-zone free and linearized digital PLL.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2006
Towards a Faster Simulation of SystemC Designs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Efficient assertion based verification using TLM.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006


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