Sofiène Tahar

Proceedings of the IEEE Symposium on Computers and Communications, 2023

A Machine Learning Based Load Value Approximator Guided by the Tightened Value Locality.

[BibT_eX]

[DOI]

Alain Aoun

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Event Tree Reliability Analysis of Safety-Critical Systems Using Theorem Proving.

[BibT_eX]

[DOI]

IEEE Syst. J., 2022

Towards All-optical Stochastic Computing Using Photonic Crystal Nanocavities.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Formalization of Functional Block Diagrams Using HOL Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods: Foundations and Applications - 25th Brazilian Symposium, 2022

On the Formalization of the Heat Conduction Problem in HOL.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 15th International Conference, 2022

On the Design of Approximate Sobel Filter.

[BibT_eX]

[DOI]

Alain Aoun

Proceedings of the International Conference on Microelectronics, 2022

Formal Probabilistic Risk Assessment of a Nuclear Power Plant.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM SIGPLAN International Workshop on Formal Techniques for Safety-Critical Systems, 2022

2021

Machine-Learning-Based Self-Tunable Design of Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Energy-Efficient Resource Allocation in Multi-UAV Networks With NOMA.

[BibT_eX]

[DOI]

Saif Najmeddin

Sonia Aïssa

IEEE Trans. Green Commun. Netw., 2021

Design Space Exploration of Stochastic Computing Architectures Implemented Using Integrated Optics.

[BibT_eX]

[DOI]

Hassnaa El-Derhalli

Sébastien Le Beux

IEEE Trans. Emerg. Top. Comput., 2021

A Quality-assured Approximate Hardware Accelerators-based on Machine Learning and Dynamic Partial Reconfiguration.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Failure Analysis of Hadoop Schedulers using an Integration of Model Checking and Simulation.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Symbolic Computation in Software Science, 2021

Optical Stochastic Computing Architectures Using Photonic Crystal Nanocavities.

[BibT_eX]

[DOI]

CoRR, 2021

Formal FT-based Cause-Consequence Reliability Analysis using Theorem Proving.

[BibT_eX]

[DOI]

CoRR, 2021

Cause-Consequence Diagram Reliability Analysis Using Formal Techniques With Application to Electrical Power Networks.

[BibT_eX]

[DOI]

IEEE Access, 2021

Energy-Efficient Wireless Powered Communications with NOMA in Multi-UAV Aided Networks.

[BibT_eX]

[DOI]

Saif Najmeddin

Sonia Aïssa

Proceedings of the 94th IEEE Vehicular Technology Conference, 2021

Formalization of RBD-Based Cause Consequence Analysis in HOL.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 14th International Conference, 2021

Dynamic Fault Tree Models for FPGA Fault Tolerance and Reliability.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

A Dynamic and Failure-Aware Task Scheduling Framework for Hadoop.

[BibT_eX]

[DOI]

IEEE Trans. Cloud Comput., 2020

Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Formal reliability and failure analysis of ethernet based communication networks in a smart grid substation.

[BibT_eX]

[DOI]

Formal Aspects Comput., 2020

ETMA: A New Software for Event Tree Analysis with Application to Power Protection.

[BibT_eX]

[DOI]

CoRR, 2020

A Formally Verified HOL4 Algebra for Event Trees.

[BibT_eX]

[DOI]

CoRR, 2020

Formal Verification of Cyber-Physical Systems using Theorem Proving (Invited Paper).

[BibT_eX]

[DOI]

Adnan Rashid

CoRR, 2020

Machine Learning-Based Self-Compensating Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Systems Conference, 2020

Decision Tree-based Adaptive Approximate Accelerators for Enhanced Quality.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Systems Conference, 2020

ETMA: An Efficient Tool for Event Trees Modeling and Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Systems Conference, 2020

A Framework for Formal Dynamic Dependability Analysis Using HOL Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 13th International Conference, 2020

Highly-Reliable Approximate Quadruple Modular Redundancy with Approximation-Aware Voting.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Microelectronics, 2020

Energy-Efficient Resource Allocation for UAV-Enabled Information and Power Transfer with NOMA.

[BibT_eX]

[DOI]

Saif Najmeddin

Sonia Aïssa

Proceedings of the IEEE Global Communications Conference, 2020

OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions.

[BibT_eX]

[DOI]

Hassnaa El-Derhalli

Sébastien Le Beux

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Probabilistic Analysis of Dynamic Fault Trees using HOL Theorem Proving.

[BibT_eX]

[DOI]

FLAP, 2019

A modeling and verification framework for optical quantum circuits.

[BibT_eX]

[DOI]

Formal Aspects Comput., 2019

Dynamic Dependability Analysis of Shuffle-exchange Networks using HOL Theorem Proving.

[BibT_eX]

[DOI]

CoRR, 2019

Integrating DFT and DRBD Formalizations in HOL4.

[BibT_eX]

[DOI]

CoRR, 2019

A Formally Verified HOL Algebra for Dynamic Reliability Block Diagrams.

[BibT_eX]

[DOI]

CoRR, 2019

Error Analysis of Approximate Array Multipliers.

[BibT_eX]

[DOI]

CoRR, 2019

On the Formalization of Importance Measures using HOL Theorem Proving.

[BibT_eX]

[DOI]

CoRR, 2019

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Methodology for the Formal Verification of Dynamic Fault Trees Using HOL Theorem Proving.

[BibT_eX]

[DOI]

IEEE Access, 2019

Energy-Efficient Resource Allocation for DAV-Enabled Wireless Powered Communications.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019

Formal Verification of Rewriting Rules for Dynamic Fault Trees.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering and Formal Methods - 17th International Conference, 2019

On the formalization of importance measures using HOL theorem proving.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Formal Methods in Software Engineering, 2019

A Formally Verified Algebraic Approach for Dynamic Reliability Block Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2019

Formal Verification of Cyber-Physical Systems Using Theorem Proving.

[BibT_eX]

[DOI]

Adnan Rashid

Proceedings of the Formal Techniques for Safety-Critical Systems, 2019

Using Machine Learning for Quality Configurable Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Stochastic Computing with Integrated Optics.

[BibT_eX]

[DOI]

Hassnaa El-Derhalli

Sébastien Le Beux

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques.

[BibT_eX]

[DOI]

Ons Lahiouel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Formal probabilistic performance verification of randomly-scheduled wireless sensor networks.

[BibT_eX]

[DOI]

Int. J. Crit. Comput. Based Syst., 2018

Formal Analysis of Discrete-Time Systems using z-Transform.

[BibT_eX]

[DOI]

FLAP, 2018

Formal Probabilistic Analysis of Dynamic Fault Trees in HOL4.

[BibT_eX]

[DOI]

CoRR, 2018

Formal Dynamic Fault Trees Analysis Using an Integration of Theorem Proving and Model Checking.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods - 10th International Symposium, 2018

Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Discriminating Chaos from Non-Gaussian Noise on Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Approximation-Conscious IC Testing.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Microelectronics, 2018

Comparative Study of Approximate Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

A bug reproduction approach based on directed model checking and crash traces.

[BibT_eX]

[DOI]

Mathieu Nayrolles

Abdelwahab Hamou-Lhadj

Alf Larsson

J. Softw. Evol. Process., 2017

Task Scheduling in Big Data Platforms: A Systematic Literature Review.

[BibT_eX]

[DOI]

J. Syst. Softw., 2017

Formal verification of stability and chaos in periodic optical systems.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2017

Exploiting bounds optimization for the semi-formal verification of analog circuits.

[BibT_eX]

[DOI]

Integr., 2017

Dynamic Fault Trees Analysis using an Integration of Theorem Proving and Model Checking.

[BibT_eX]

[DOI]

CoRR, 2017

Detection and sizing of metal-loss defects in oil and gas pipelines using pattern-adapted wavelets and machine learning.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2017

Intertwined Global Optimization Based Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2017

Formalization of Birth-Death and IID processes in higher-order logic.

[BibT_eX]

[DOI]

Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Formal Analysis of Information Flow in HOL.

[BibT_eX]

[DOI]

Proceedings of the Dependable Software Engineering. Theories, Tools, and Applications, 2017

Enhancing analog yield optimization for variation-aware circuits sizing.

[BibT_eX]

[DOI]

Ons Lahiouel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Enhancing Model Order Reduction for Nonlinear Analog Circuit Simulation.

[BibT_eX]

[DOI]

Henda Aridhi

IEEE Trans. Very Large Scale Integr. Syst., 2016

Tuning framework for stencil computation in heterogeneous parallel platforms.

[BibT_eX]

[DOI]

Taieb Lamine Ben Cheikh

Alexandra Aguiar

Gabriela Nicolescu

J. Supercomput., 2016

Formalization of Reliability Block Diagrams in Higher-order Logic.

[BibT_eX]

[DOI]

J. Appl. Log., 2016

On the formal analysis of Gaussian optical systems in HOL.

[BibT_eX]

[DOI]

Formal Aspects Comput., 2016

Formal Probabilistic Analysis of Lifetime for a WSN-based Monitoring Application.

[BibT_eX]

[DOI]

Proceedings of the 10th Workshop on Verification and Evaluation of Computer and Communication System, 2016

Hierarchical Verification of Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods - 8th International Symposium, 2016

Formalization of Normal Random Variables in HOL.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 9th International Conference, 2016

Formal Dependability Modeling and Analysis: A Survey.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - 9th International Conference, 2016

Cross recurrence verification technique for process variation-resilient analog circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Formal Probabilistic Analysis of a WSN-Based Monitoring Framework for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques for Safety-Critical Systems, 2016

Formal Analysis of Engineering Systems Based on Signal-Flow-Graph Theory.

[BibT_eX]

[DOI]

Proceedings of the Numerical Software Verification - 9th International Workshop, 2016

2015

On the Formalization of Cardinal Points of Optical Systems.

[BibT_eX]

[DOI]

Proceedings of the Formalisms for Reuse and Systems Integration, 2015

Lyapunov-Based Adaptive State of Charge and State of Health Estimation for Lithium-Ion Batteries.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2015

Evaluation of anonymity and confidentiality protocols using theorem proving.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2015

Formal probabilistic analysis of detection properties in wireless sensor networks.

[BibT_eX]

[DOI]

Formal Aspects Comput., 2015

Predicting Scheduling Failures in the Cloud.

[BibT_eX]

[DOI]

CoRR, 2015

Formal reliability analysis of wireless sensor network data transport protocols using HOL.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Wireless and Mobile Computing, 2015

JCHARMING: A bug reproduction approach using crash traces and directed model checking.

[BibT_eX]

[DOI]

Mathieu Nayrolles

Abdelwahab Hamou-Lhadj

Alf Larsson

Proceedings of the 22nd IEEE International Conference on Software Analysis, 2015

Formal modeling and verification of integrated photonic systems.

[BibT_eX]

[DOI]

Valdivino Alexandre de Santiago Jr.

Proceedings of the Annual IEEE Systems Conference, 2015

Time Performance Formal Evaluation of Complex Systems.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods: Foundations and Applications - 18th Brazilian Symposium, 2015

Towards the Formalization of Fractional Calculus in Higher-Order Logic.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2015

Enabling Symbolic and Numerical Computations in HOL Light.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2015

Formalizing Physics: Automation, Presentation and Foundation Issues.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2015

Towards Formal Reliability Analysis of Logistics Service Supply Chains using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the IWIL@LPAR 2015, 2015

Self-Organizing Map-Based Feature Visualization and Selection for Defect Depth Estimation in Oil and Gas Pipelines.

[BibT_eX]

[DOI]

Abduljalil Mohamed

Proceedings of the 19th International Conference on Information Visualisation, 2015

A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal Designs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

ATLAS: An AdapTive faiLure-Aware Scheduler for Hadoop.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Performance Computing and Communications Conference, 2015

Formal Analysis of Power Electronic Systems.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2015

Predicting Scheduling Failures in the Cloud: A Case Study with Google Clusters and Hadoop on Amazon EMR.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

On the Formal Analysis of Photonic Signal Processing Systems.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Industrial Critical Systems, 2015

On the Formal Verification of Optical Quantum Gates in HOL.

[BibT_eX]

[DOI]

Prakash Panangaden

Proceedings of the Formal Methods for Industrial Critical Systems, 2015

A Machine Learning Approach for Big Data in Oil and Gas Pipelines.

[BibT_eX]

[DOI]

Abduljalil Mohamed

Proceedings of the 3rd International Conference on Future Internet of Things and Cloud, 2015

Towards enhancing analog circuits sizing using SMT-based techniques.

[BibT_eX]

[DOI]

Ons Lahiouel

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Design and verification of a frequency domain equalizer.

[BibT_eX]

[DOI]

Anis Souari

Mohamed Lassaad Ammari

Microelectron. J., 2014

Formal Analysis of Optical Systems.

[BibT_eX]

[DOI]

Sanaz Khan Afshar

Math. Comput. Sci., 2014

An approach for lifetime reliability analysis using theorem proving.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2014

Formalization of Zsyntax to Reason About Molecular Pathways in HOL4.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods: Foundations and Applications - 17th Brazilian Symposium, 2014

On the Quantum Formalization of Coherent Light in HOL.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods - 6th International Symposium, NFM 2014, Houston, TX, USA, April 29, 2014

Enablingy the DC solutions characterization using a fuzzy approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Towards the formal verification of optical interconnects.

[BibT_eX]

[DOI]

Sanaz Khan Afshar

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A Framework for Formal Reasoning about Geometrical Optics.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2014

Towards the Formal Reliability Analysis of Oil and Gas Pipelines.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2014

Formalization of Complex Vectors in Higher-Order Logic.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computer Mathematics - International Conference, 2014

On the Formalization of Z-Transform in HOL.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving - 5th International Conference, 2014

Formal Verification of Optical Quantum Flip Gate.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving - 5th International Conference, 2014

Implicational Rewriting Tactics in HOL.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving - 5th International Conference, 2014

Towards ray optics formalization of optical imaging systems.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Information Reuse and Integration, 2014

On the Formal Analysis of HMM Using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2014

Formal reliability analysis of a typical FHIR standard based e-Health system using PRISM.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on e-Health Networking, 2014

Generation of reduced analog circuit models using transient simulation traces.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A qualitative simulation approach for verifying PLL locking property.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A semi-formal approach for analog circuits behavioral properties verification.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Towards the formal analysis of microresonators based photonic systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A survey on the application of Neural Networks in the safety assessment of oil and gas pipelines.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Symposium on Computational Intelligence for Engineering Solutions, 2014

Performance evaluation of time and frequency domain equalizers.

[BibT_eX]

[DOI]

Anis Souari

Mohamed Lassaad Ammari

Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

Real time verification of firewalls with dynamic rulebase update.

[BibT_eX]

[DOI]

Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013

Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formalization of Measure Theory and Lebesgue Integration for Probabilistic Analysis in HOL.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Formal Reasoning About Finite-State Discrete-Time Markov Chains in HOL.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

Towards the Formal Performance Analysis of Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 2013 Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2013

Formal Analysis of Memory Contention in a Multiprocessor System.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods: Foundations and Applications - 16th Brazilian Symposium, 2013

Formal Analysis of Information Flow Using Min-Entropy and Belief Min-Entropy.

[BibT_eX]

[DOI]

Ghassen Helali

Proceedings of the Formal Methods: Foundations and Applications - 16th Brazilian Symposium, 2013

Formal Stability Analysis of Optical Resonators.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods, 2013

Formalization of Infinite Dimension Linear Spaces with Application to Quantum Theory.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods, 2013

Formal Reasoning about Classified Markov Chains in HOL.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving - 4th International Conference, 2013

2012

Formal Probabilistic Analysis of a Wireless Sensor Network for Forest Fire Detection.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012

On the Verification of a WiMax Design Using Symbolic Simulation.

[BibT_eX]

[DOI]

Salim Ismail Al-Akhras

Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012

Formal Analysis of Soft Errors using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012

Formal error analysis and verification of a frequency domain equalizer.

[BibT_eX]

[DOI]

Anis Souari

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Using LCSS algorithm for circuit level verification of analog designs.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs.

[BibT_eX]

[DOI]

Taieb Lamine Ben Cheikh

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Quantitative Analysis of Information Flow Using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2012

Verifying jitter in an analog and mixed signal design using dynamic time warping.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Towards improving simulation of analog circuits using model order reduction.

[BibT_eX]

[DOI]

Henda Aridhi

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Formal verification of the heavy hitter problem.

[BibT_eX]

[DOI]

Ghassen Helali

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

Novel algorithm for detecting conflicts in firewall rules.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

On the Formal Analysis of Geometrical Optics in HOL.

[BibT_eX]

[DOI]

Proceedings of the Automated Deduction in Geometry - 9th International Workshop, 2012

2011

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

NuMDG: A New Tool for Multiway Decision Graphs Construction.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2011

Reasoning about conditional probabilities in a higher-order-logic theorem prover.

[BibT_eX]

[DOI]

J. Appl. Log., 2011

Formal reliability analysis of combinational circuits using theorem proving.

[BibT_eX]

[DOI]

Jigar Patel

J. Appl. Log., 2011

Formal verification of bond graph modelled analogue circuits.

[BibT_eX]

[DOI]

William Denman

IET Circuits Devices Syst., 2011

Towards Flight Control Verification Using Automated Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods, 2011

Formalization of Entropy Measures in HOL.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving - Second International Conference, 2011

Modeling and verification of firewall configurations using domain restriction method.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference for Internet Technology and Secured Transactions, 2011

Formal Analysis of a Scheduling Algorithm for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2011

Welcome to ICCD 2011!

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching.

[BibT_eX]

[DOI]

Rajeev Narayanan

Proceedings of the Design, Automation and Test in Europe, 2011

Formalization of Finite-State Discrete-Time Markov Chains in HOL.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2011

2010

Formal Reliability Analysis Using Theorem Proving.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Formally Analyzing Expected Time Complexity of Algorithms Using Theorem Proving.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2010

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits.

[BibT_eX]

[DOI]

Rajeev Narayanan

J. Electron. Test., 2010

Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL.

[BibT_eX]

[DOI]

Comput. J., 2010

Formal Lifetime Reliability Analysis Using Continuous Random Variables.

[BibT_eX]

[DOI]

Proceedings of the Logic, 2010

On the Formalization of the Lebesgue Integration Theory in HOL.

[BibT_eX]

[DOI]

Proceedings of the Interactive Theorem Proving, First International Conference, 2010

Welcome to ICCD 2010!

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Formal verification of analog circuits in the presence of noise and process variation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

10271 Abstracts Collection - Verification over discrete-continuous boundaries.

[BibT_eX]

[DOI]

Proceedings of the Verification over discrete-continuous boundaries, 04.07. - 09.07.2010, 2010

Formal Probabilistic Analysis: A Higher-Order Logic Based Approach.

[BibT_eX]

[DOI]

Proceedings of the Abstract State Machines, 2010

Performance analysis of real-time rewriting models.

[BibT_eX]

[DOI]

Proceedings of the 8th ACS/IEEE International Conference on Computer Systems and Applications, 2010

2009

Performance Analysis and Functional Verification of the Stop-and-Wait Protocol in HOL.

[BibT_eX]

[DOI]

J. Autom. Reason., 2009

Integrating Abstraction Techniques for Formal Verification of Analog Designs.

[BibT_eX]

[DOI]

J. Aerosp. Comput. Inf. Commun., 2009

Rank Functions Based Inference System for Group Key Management Protocols Verification.

[BibT_eX]

[DOI]

Adel Bouhoula

Int. J. Netw. Secur., 2009

Formal Analysis of Optical Waveguides in HOL.

[BibT_eX]

[DOI]

Sanaz Khan Afshar

Proceedings of the Theorem Proving in Higher Order Logics, 22nd International Conference, 2009

Radio Access Network traffic generation for Mobile Switching Center.

[BibT_eX]

[DOI]

Suliman Albasheir

Claude Gauthier

Jean Roussel Personna

Proceedings of the 14th IEEE Symposium on Computers and Communications (ISCC 2009), 2009

Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays.

[BibT_eX]

[DOI]

Proceedings of the Integrated Formal Methods, 7th International Conference, 2009

Formal verification of analog designs using MetiTarski.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Formal Reasoning about Expectation Properties for Continuous Random Variables.

[BibT_eX]

[DOI]

Proceedings of the FM 2009: Formal Methods, 2009

2008

IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.

[BibT_eX]

[DOI]

Aijiao Cui

Chip-Hong Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Formal verification of analog and mixed signal designs: A survey.

[BibT_eX]

[DOI]

Guy Bois

Microelectron. J., 2008

Formal verification of ASMs using MDGs.

[BibT_eX]

[DOI]

Kirsten Winter

J. Syst. Archit., 2008

Using Theorem Proving to Verify Expectation and Variance for Discrete Random Variables.

[BibT_eX]

[DOI]

J. Autom. Reason., 2008

Probabilistic Analysis of Wireless Systems Using Theorem Proving.

[BibT_eX]

[DOI]

Abu Nasser Mohammed Abdullah

Proceedings of the First Workshop on Formal Methods for Wireless Systems, 2008

Error Analysis and Verification of an IEEE 802.11 OFDM Modem using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Formal Methods for Wireless Systems, 2008

Event-B based invariant checking of secrecy in group key protocols.

[BibT_eX]

[DOI]

Leila Jemni Ben Ayed

Proceedings of the LCN 2008, 2008

Performance Analysis of ARQ Protocols using a Theorem Prover.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

A New Approach for the Construction of Multiway Decision Graphs.

[BibT_eX]

[DOI]

Proceedings of the Theoretical Aspects of Computing, 2008

Fragile IP Watermarking Techniques.

[BibT_eX]

[DOI]

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007

Formalization of the Standard Uniform random variable.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2007

A Design for Verification Approach Using an Embedding of PSL in aSML.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2007

Error analysis of digital filters using HOL theorem proving.

[BibT_eX]

[DOI]

J. Appl. Log., 2007

Formal Specification and Verification of the Intrusion-Tolerant Enclaves Protocol.

[BibT_eX]

[DOI]

Jozef Hooman

Int. J. Netw. Secur., 2007

Providing a formal linkage between MDG and HOL.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2007

Verification of Expectation Properties for Discrete Random Variables in HOL.

[BibT_eX]

[DOI]

Proceedings of the Theorem Proving in Higher Order Logics, 20th International Conference, 2007

Qualitative Abstraction based Verification for Analog Circuits.

[BibT_eX]

[DOI]

Guy Bois

Proceedings of the ISoLA 2007, 2007

Verification of Probabilistic Properties in HOL Using the Cumulative Distribution Function.

[BibT_eX]

[DOI]

Proceedings of the Integrated Formal Methods, 6th International Conference, 2007

Formal Verification of Analog and Mixed Signal Designs in Mathematica.

[BibT_eX]

[DOI]

Ghiath Al Sammane

Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

Autometic Generation of SystemC Transactors from AsmL Specification.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

A symbolic methodology for the verification of analog and mixed signal designs.

[BibT_eX]

[DOI]

Ghiath Al Sammane

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Formalization of Continuous Probability Distributions.

[BibT_eX]

[DOI]

Proceedings of the Automated Deduction, 2007

Rank Theorems for Forward Secrecy in Group Key Management Protocols.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006

Design and verification of SystemC transaction-level models.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

An approach for the formal verification of DSP designs using Theorem proving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Hybrid verification integrating HOL theorem proving with MDG model checking.

[BibT_eX]

[DOI]

Rabeb Mizouni

Microelectron. J., 2006

Towards a Faster Simulation of SystemC Designs.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

A practical approach for monitoring analog circuits.

[BibT_eX]

[DOI]

Guy Bois

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Design for Verification of the PCI-X Bus.

[BibT_eX]

[DOI]

Haja Moinudeen

Abu Nasser Mohammed Abdullah

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Formal Analysis and Verification of an OFDM Modem Design using HOL.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

On the numerical verification of probabilistic rewriting systems.

[BibT_eX]

[DOI]

Jounaïdi Ben Hassen

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient assertion based verification using TLM.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Generating finite state machines from SystemC.

[BibT_eX]

[DOI]

Haja Moinudeen

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Finite State Machine IP Watermarking: A Tutorial.

[BibT_eX]

[DOI]

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005

Formalization of Fixed-Point Arithmetic in HOL.

[BibT_eX]

[DOI]

Abdelkader Dekdouk

Formal Methods Syst. Des., 2005

On the Transformation of SystemC to AsmL Using Abstract Interpretation.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Abstract Interpretation of Object-oriented Languages, 2005

On the formal verification of a SystemC Packet switch model.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Design for Verification of SystemC Transaction Level Models.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A Public-Key Watermarking Technique for IP Designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

An Approach for the Verification of SystemC Designs Using AsmL.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2005

AsmL Semantics in Fixpoint.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Abstract State Machines, 2005

Embedding and Verification of PSL using AsmL.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Abstract State Machines, 2005

2004

MDG-Based State Enumeration By Retiming And Circuit Transformation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

A Survey on IP Watermarking Techniques.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2004

Error Analysis of Digital Filters Using Theorem Proving.

[BibT_eX]

[DOI]

Proceedings of the Theorem Proving in Higher Order Logics, 17th International Conference, 2004

Design for verification of a PCI bus in SystemC.

[BibT_eX]

[DOI]

Karim Oumalou

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Assertion based verification of PSL for SystemC designs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Formal verification of an SoC platform protocol converter.

[BibT_eX]

Jounaïdi Ben Hassen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Towards an efficient assertion based verification of SystemC designs.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

A Methodology for the Formal Verification of FFT Algorithms in HOL.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Enabling SystemC Verification using Abstract State Machines.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2004

On the Design and Verification Methodology of the Look-Aside Interface.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

First-Order LTL Model Checking Using MDGs.

[BibT_eX]

[DOI]

Fang Wang

Otmane Aït Mohamed

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

Providing Automated Verification in HOL Using MDGs.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2003

Comparison of SPIN and VIS for protocol verification.

[BibT_eX]

[DOI]

Ferhat Khendek

Int. J. Softw. Tools Technol. Transf., 2003

Hierarchical formal verification using a hybrid tool.

[BibT_eX]

[DOI]

Skander Kort

Int. J. Softw. Tools Technol. Transf., 2003

Formal Verification of ASM Designs Using the MDG Tool.

[BibT_eX]

[DOI]

Kirsten Winter

Proceedings of the 1st International Conference on Software Engineering and Formal Methods (SEFM 2003), 2003

A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

IP Watermarking Techniques: Survey and Comparison.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Compositional Verification of a Switch Fabric from Nortel Networks.

[BibT_eX]

[DOI]

Yassine Mokhtari

Proceedings of the Formal Methods and Software Engineering, 2003

Modeling System C Fixed-Point Arithmetic in HOL.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2003

Language emptiness checking using MDGs.

[BibT_eX]

[DOI]

Fang Wang

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

The Application of Formal Verification to SPW Designs.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

On the Correctness of an Intrusion-Tolerant Group Communication Protocol.

[BibT_eX]

[DOI]

Jozef Hooman

Proceedings of the Correct Hardware Design and Verification Methods, 2003

Interfacing ASM with the MDG Tool.

[BibT_eX]

[DOI]

Kirsten Winter

Proceedings of the Abstract State Machines, 2003

2002

Formally Linking MDG and HOL Based on a Verified MDG System.

[BibT_eX]

[DOI]

Proceedings of the Integrated Formal Methods, Third International Conference, 2002

Formalization of Cadence SPW Fixed-Point Arithmetic in HOL.

[BibT_eX]

[DOI]

Abdelkader Dekdouk

Proceedings of the Integrated Formal Methods, Third International Conference, 2002

Formal Verification of a SONET Telecom System Block.

[BibT_eX]

[DOI]

M. Hasan Zobair

Proceedings of the Formal Methods and Software Engineering, 2002

Enabling Hardware Verification through Design Changes.

[BibT_eX]

[DOI]

John Harrison

Proceedings of the Formal Methods and Software Engineering, 2002

Environment Synthesis for Compositional Model Checking.

[BibT_eX]

[DOI]

Yassine Mokhtari

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Formal Verification of a DSP Chip Using an Iterative Approach.

[BibT_eX]

[DOI]

Adel Ghazel

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

Performance of various multistage interference cancellation schemes for asynchronous QPSK/DS/CDMA over multipath Rayleigh fading channels.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2001

Practical approaches to the verification of a telecom megacell using FormalCheck.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Hierarchical Verification Using an MDG-HOL Hybrid Tool.

[BibT_eX]

[DOI]

Iskander Kort

Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000

Multilevel quantized soft-limiting detector for an FH-SSMA system.

[BibT_eX]

[DOI]

J. Commun. Networks, 2000

An analytical model for performance evaluation of parallel interference cancellers in CDMA systems.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2000

Sequential and Distributed Simulations Using Java Threads.

[BibT_eX]

[DOI]

Mostafa Azizi

Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

SPIN vs. VIS: A Case Study on the Formal Verification of the ATMR Protocol.

[BibT_eX]

[DOI]

Ferhat Khendek

Proceedings of the 3rd IEEE International Conference on Formal Engineering Methods, 2000

Analysis of Multilevel-Quantized Soft-Limiting Detector for an FH-SSMA System.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000

Formal hardware verification by integrating HOL and MDG.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999

Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Comparing HOL and MDG: a Case Study on the Verification of an ATM Switch Fabric.

[BibT_eX]

Nord. J. Comput., 1999

Adaptive multistage parallel interference cancellation for CDMA.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 1999

Multistage interference cancellation with diversity reception for asynchronous QPSK DS/CDMA systems over multipath fading channels.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 1999

Importing MDG Verification Results into HOL.

[BibT_eX]

[DOI]

Haiyan Xiong

Proceedings of the Theorem Proving in Higher Order Logics, 12th International Conference, 1999

Multithreading-based Coverification Technique of HW/SW Systems.

[BibT_eX]

Mostafa Azizi

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Multistage interference cancellation with diversity reception for QPSK asynchronous DS/CDMA system over multipath fading channels.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999

A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs.

[BibT_eX]

[DOI]

Subhashini Balakrishnan

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

A Practical Methodology for the Formal Verification of RISC Processors.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1998

Model checking of a real ATM switch.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS.

[BibT_eX]

[DOI]

Jianping Lu

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Three Approaches to Hardware Verification: HOL, MDG and VIS Compared.

[BibT_eX]

[DOI]

Jianping Lu

Proceedings of the Formal Methods in Computer-Aided Design, 1998

1997

Verification with Abstract State Machines Using MDGs.

[BibT_eX]

[DOI]

Proceedings of the Formal Hardware Verification - Methods and Systems in Comparison, 1997

1996

A Comparison of MDG and HOL for Hardware Verification.

[BibT_eX]

[DOI]

Proceedings of the Theorem Proving in Higher Order Logics, 9th International Conference, 1996

Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

MDG Tools for the Verification of RTL Designs.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Formal Specification and Verification Techniques for RISC Pipeline Conflicts.

[BibT_eX]

[DOI]

Comput. J., 1995

Eine Methode zur formalen Verifikation von RISC-Prozessoren.

[BibT_eX]

[DOI]

PhD thesis, 1995

1994

Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL.

[BibT_eX]

[DOI]

Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1994

Formal verification of pipeline conflicts in RISC processors.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

Implementing a Methodology for Formally Verifying RISC Processors in HOL.

[BibT_eX]

[DOI]

Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

Towards a Methodology for the Formal Hierarchical Verification.

[BibT_eX]

[DOI]