Amin Ansari

According to our database1, Amin Ansari authored at least 30 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
EGA-Depth: Efficient Guided Attention for Self-Supervised Multi-Camera Depth Estimation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2021
X-Distill: Improving Self-Supervised Monocular Depth via Cross-Task Distillation.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

2019
Vehicle Detection With Automotive Radar Using Deep Learning on Range-Azimuth-Doppler Tensors.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

2017
Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2014
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Illusionist: Transforming lightweight cores into aggressive cores on demand.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2011
Overcoming Hard-Faults in High-Performance Microprocessors.
PhD thesis, 2011

StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs.
IEEE Trans. Computers, 2011

Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines.
IEEE Trans. Computers, 2011

Bundled execution of recurring traces for energy-efficient general purpose processing.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Encore: low-cost, fine-grained transient fault recovery.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Archipelago: A polymorphic cache design for enabling robust near-threshold operation.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Putting Faulty Cores to Work.
IEEE Micro, 2010

Erasing Core Boundaries for Robust and Configurable Performance.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Necromancer: enhancing system throughput by animating dead cores.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

Shoestring: probabilistic soft error reliability on the cheap.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

CoreGenesis: erasing core boundaries for robust and configurable performance.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Parade: A versatile parallel architecture for accelerating pulse train clustering.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

ZerehCache: armoring cache architectures in high defect density technologies.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Enabling ultra low voltage system operation by tolerating on-chip cache failures.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Adaptive online testing for efficient hard fault detection.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Verification of Peterson's Algorithm for Leader Election in a Unidirectional Asynchronous Ring Using NuSMV
CoRR, 2008

The StageNet fabric for constructing resilient multicore systems.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems.
Proceedings of the 2008 International Conference on Compilers, 2008


  Loading...