Janarbek Matai

According to our database1, Janarbek Matai authored at least 23 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Restoring the Broken Covenant Between Compilers and Deep Learning Accelerators.
CoRR, 2023

Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architectures.
CoRR, 2023

Factorized Inverse Path Tracing for Efficient and Accurate Material-Lighting Estimation.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

2022
IRISformer: Dense Vision Transformers for Single-Image Inverse Rendering in Indoor Scenes.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
Real-Time and Accurate Self-Supervised Monocular Depth Estimation on Mobile Device.
Proceedings of the NeurIPS 2021 Competitions and Demonstrations Track, 2021

X-Distill: Improving Self-Supervised Monocular Depth via Cross-Task Distillation.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

2018
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Parallel Programming for FPGAs.
CoRR, 2018

2016
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Composable, parameterizable templates for high-level synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Templates and Patterns : Augmenting High-Level Synthesis for Domain-Specific Computing.
PhD thesis, 2015

Quantifying Timing-Based Information Flow in Cryptographic Hardware.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Enabling FPGAs for the Masses.
CoRR, 2014

Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

High throughput channel tracking for JTRS wireless channel emulation.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Energy efficient canonical huffman encoding.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A low-power Adaboost-based object detection processor using Haar-like features.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

2012
Designing a hardware in the loop wireless digital channel emulator for software defined radio.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Design and Implementation of an FPGA-Based Real-Time Face Recognition System.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2009
Connection Framework of RT-Middleware and CAMUS for Maintaining Ubiquity between Two Ubiquitous Robot Spaces.
Adv. Robotics, 2009

2008
Integration framework for interoperability of distributed and heterogeneous robot middlewares.
Proceedings of the 10th International Conference on Control, 2008

2007
Learning-Based Trust Model for Optimization of Selecting Web Services.
Proceedings of the Advances in Data and Web Management, 2007


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