Amitabh Chatterjee

According to our database, Amitabh Chatterjee authored at least 6 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

SPICE level implementation of physics of filamentation in ESD protection devices.

Dheeraj Kumar Sinha, Amitabh Chatterjee

Microelectron. Reliab., 2017

2016

A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET.

Dheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav, Gaurav Trivedi, Victor Koldyaev

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach.

Vishnuram Abhinav, Dheeraj Kumar Sinha, Amitabh Chatterjee, Forrest Brewer

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding.

Mohd. Tasleem Khan, Shaik Rafi Ahamed, Amitabh Chatterjee

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A methodology for designing LVDS interface system.

Jayshree, Seema Verma, Amitabh Chatterjee

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

Methodology for optimizing ESD protection for high speed LVDS based I/Os.

Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015