Mohd. Tasleem Khan
Orcid: 0000-0001-6106-1534
According to our database1,
Mohd. Tasleem Khan
authored at least 26 papers
between 2016 and 2024.
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Bibliography
2024
Application of Distributed Arithmetic to Adaptive Filtering Algorithms: Trends, Challenges and Future.
CoRR, 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Trans. Instrum. Meas., 2023
Analyzing Step-Size Approximation for Fixed-Point Implementation of LMS and BLMS Algorithms.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
2022
An Efficient Scheme for Acoustic Echo Canceller Implementation Using Offset Binary Coding.
IEEE Trans. Instrum. Meas., 2022
High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Two Distributed Arithmetic Based High Throughput Architectures of Non-Pipelined LMS Adaptive Filters.
IEEE Access, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
2021
High-Throughput and Improved-Convergent Design of Pipelined Adaptive DFE for 5G Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
High-Performance Hardware Design of Block LMS Adaptive Noise Canceller for In-Ear Headphones.
IEEE Consumer Electron. Mag., 2020
2019
Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IET Comput. Digit. Tech., 2019
Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT.
Proceedings of the National Conference on Communications, 2019
2018
Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter.
IET Circuits Devices Syst., 2018
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Analysis and Implementation of Block Least Mean Square Adaptive Filter using Offset Binary Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016