Forrest Brewer

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

Design and Analysis of Collective Pulse Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Direct ΣΔ Bitstream Processing for High Performance Feedback Control.

[BibT_eX]

[DOI]

Joseph Poverelli

Proceedings of the 2019 IEEE Conference on Control Technology and Applications, 2019

2018

Impolite High Speed Interfaces with Asynchronous Pulse Logic.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic.

[BibT_eX]

[DOI]

Mohd. Tasleem Khan

Shaik Rafi Ahamed

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Design and analysis of high performance pulse ring VCO.

[BibT_eX]

[DOI]

Aditya Dalakoti

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Low phase noise pulse rotary wave voltage controlled oscillator.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

High performance pulse ring voltage controlled oscillator for Internet of Things.

[BibT_eX]

[DOI]

Aditya Dalakoti

Proceedings of the International SoC Design Conference, 2017

Pulse Ring Oscillator Tuning via Pulse Dynamics.

[BibT_eX]

[DOI]

Aditya Dalakoti

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links.

[BibT_eX]

[DOI]

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2013

Ongoing challenges in automated cyberphysical cross-domain design.

[BibT_eX]

[DOI]

Kunal Arya

Joseph Poverelli

Proceedings of the International Conference on Computing, Networking and Communications, 2013

Formal verification of analog circuit parameters across variation utilizing SAT.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

A hierarchical Ant-Colony heuristic for architecture synthesis for on-chip communication.

[BibT_eX]

[DOI]

Wei Tang

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2011

Automated MAC Protocol Generation with Multiple Neighborhoods and Acknowledgments Based on Symbolic Monte Carlo Simulation.

[BibT_eX]

[DOI]

Jian Zhen

Muralidaran Vijayaraghavan

Volkan Rodoplu

Proceedings of the Global Communications Conference, 2011

2010

Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID).

[BibT_eX]

[DOI]

Joel S. Emer

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

A Methodology for Optimal MAC Protocol Generation: Case Study of a Synchronous MAC Channel.

[BibT_eX]

[DOI]

Jian Zhen

Volkan Rodoplu

Proceedings of the Global Communications Conference, 2010

2009

Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

2009 MEMOCODE Co-Design Contest.

[BibT_eX]

[DOI]

James C. Hoe

Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Control design for force balance sensors.

[BibT_eX]

[DOI]

Proceedings of the American Control Conference, 2009

2008

Structural integrity: safety in miniature technology.

[BibT_eX]

[DOI]

SIGBED Rev., 2008

Advances in ESL Design.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Latency-Insensitive Hardware/Software Interfaces.

[BibT_eX]

[DOI]

Chris Gill

Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Pulse-mode link for robust, high speed communications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Synthesizing Synchronous Elastic Flow Networks.

[BibT_eX]

[DOI]

Carlos Jorge Ferreira Silvestre

Proceedings of the Design, Automation and Test in Europe, 2008

Computationally efficient methods for digital control.

[BibT_eX]

[DOI]

Duarte Antunes

João Pedro Hespanha

Nitin Kataria

Proceedings of the 47th IEEE Conference on Decision and Control, 2008

2007

MEMOCODE 2007 Co-Design Contest.

[BibT_eX]

[DOI]

James C. Hoe

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Towards understanding architectural tradeoffs in MEMS closed-loop feedback control.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Compilers, 2007

2006

Layout driven data communication optimization for high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A case study of multi-threading in the embedded space.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Compilers, 2006

Extensible control architectures.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Compilers, 2006

2005

PyPBS design and methodologies.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Weighted control scheduling.

[BibT_eX]

[DOI]

Aravind Vijayakumar

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

RTL SAT simplification by Boolean and interval arithmetic reasoning.

[BibT_eX]

[DOI]

Ganapathy Parthasarathy

Madhu K. Iyer

Kwang-Ting Cheng

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Wirelength optimization by optimal block orientation.

[BibT_eX]

[DOI]

Xin Hao

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Structural search for RTL with predicate learning.

[BibT_eX]

[DOI]

Ganapathy Parthasarathy

Madhu K. Iyer

Kwang-Ting Cheng

Malgorzata Marek-Sadowska

Proceedings of the 42nd Design Automation Conference, 2005

2003

Buffer delay change in the presence of power and ground noise.

[BibT_eX]

[DOI]

Lauren Hui Chen

IEEE Trans. Very Large Scale Integr. Syst., 2003

Nano, quantum, and molecular computing: are we ready for the validation and test challenges?

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002

Symbolic NFA scheduling of a RISC microprocessor.

[BibT_eX]

[DOI]

Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2002

Coping with buffer delay change due to power and ground noise.

[BibT_eX]

[DOI]

Lauren Hui Chen

Proceedings of the 39th Design Automation Conference, 2002

2001

Automata-Based Symbolic Scheduling for Looping DFGs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

2000

AQUILA: An Equivalence Checking System for Large Sequential Designs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Representing and Scheduling Looping Behavior Symbolically.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Power and signal integrity improvement in ultra high-speed current mode logic.

[BibT_eX]

[DOI]

Hien Ha

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Shape-based sequential machine analysis.

[BibT_eX]

[DOI]

Andrew Crews

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Model for Scheduling Protocol-Constrained Components and Environments.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Efficient encoding for exact symbolic automata-based scheduling.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Scheduling and binding bounds for RT-level symbolic execution.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

A new symbolic technique for control-dependent scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Clock skew optimization for ground bounce control.

[BibT_eX]

[DOI]

Ashok Vittal

Hein Ha

Malgorzata Marek-Sadowska

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Controller optimization for protocol intensive applications.

[BibT_eX]

[DOI]

Andrew Crews

Proceedings of the conference on European design automation, 1996

Implementation of an Efficient Parallel BDD Package.

[BibT_eX]

[DOI]

Tony Stornetta

Proceedings of the 33st Conference on Design Automation, 1996

Concurrent Analysis Techniques for Data Path Timing Optimization.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Symbolic Scheduling Techniques.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 1995

Analysis of conditional resource sharing using a guard-based control representation.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Symbolic execution of data paths.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

On applicability of symbolic techniques to larger scheduling problems.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Symbolic Modeling and Evaluation of Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

Clairvoyant: a synthesis system for production-based specification.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Ensemble representation and techniques for exact control-dependent scheduling.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Incorporating Speculative Execution in Exact Control-Dependent Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

High-Level Symbolic Construction Technique for High Performance Sequential Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

High performance data-path synthesis via communication metrics.

[BibT_eX]

[DOI]

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Interface constrained processor specification and scheduling.

[BibT_eX]

[DOI]

Jack Greenbaum

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Synthesis from Production-Based Specifications.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

DISC: Dynamic Instruction Stream Computer.

[BibT_eX]

[DOI]

Mario Nemirovsky

Roger C. Wood

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Relevant Issues in High-Level Connectivity Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

Chippe: a system for constraint driven behavioral synthesis.

[BibT_eX]

[DOI]

Daniel D. Gajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Interconnection synthesis with geometric constraints.

[BibT_eX]

[DOI]

Barry M. Pangrle

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1988

Constraint Driven Behavioral Synthesis

[BibT_eX]

[DOI]

PhD thesis, 1988

1987

Knowledge Based Control in Micro-Architecture Design.

[BibT_eX]

[DOI]

Daniel Gajski

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

An expert-system paradigm for design.

[BibT_eX]

[DOI]