André Borin Soares

According to our database1, André Borin Soares authored at least 14 papers between 2004 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Adaptive Shared Memory Control for Multimedia Systems-on-Chip.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

H.264 8x8 inverse transform architecture optimization.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues.
Int. J. Reconfigurable Comput., 2013

2012
Towards an Efficient Memory Architecture for Video Decoding Systems.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

2011
Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2008
A new march sequence to fit DDR SDRAM test in burst mode.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2006
Automatic generation of neural networks for image processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable communications for image processing applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Contextual Resources use: a Proof of Concept through the APACHES' Platform.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Gradient pile up for edge detection on hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Time and energy efficient mapping of embedded applications onto NoCs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Gradient Pile up Algorithm for Edge Enhancement and Detection.
Proceedings of the Image Analysis and Recognition: International Conference, 2004


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