Gilles Sassatelli

According to our database1, Gilles Sassatelli authored at least 140 papers between 1999 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
PoETE: A Method to Design Temperature-Aware Integrated Systems.
J. Low Power Electronics, 2018

Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Fine-grained monitoring for self-aware embedded systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Roundabout: A Network-on-Chip router with adaptive buffer sharing.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Embedded systems to high performance computing using STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures.
IEEE Trans. Computers, 2016

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices.
JETC, 2016

Exploring MRAM Technologies for Energy Efficient Systems-On-Chip.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures.
CoRR, 2016

Speed and accuracy dilemma in NoC simulation: What about memory impact?
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural Networks.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Design space exploration for complex automotive applications: an engine control system case study.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

2015
A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Adaptive Power monitoring for self-aware embedded systems.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Potential applications based on NVM emerging technologies.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A trace-driven approach for fast and accurate simulation of manycore architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Power efficient Thermally Assisted Switching Magnetic memory based memory systems.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Method for dynamic power monitoring on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embedded Comput. Syst., 2013

Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Message from the general and program chairs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Trends on the application of emerging nonvolatile memory to processors and programmable devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Instruction-driven timing CPU model for efficient embedded software development using OVP.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Multi-level MPSoC modeling for reducing software development cycle.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Simultaneous multithreading support in embedded distributed memory MPSoCs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization.
TRETS, 2012

A Mobile Computing Framework for Pervasive Adaptive Platforms.
IJDSN, 2012

Accuracy evaluation of GEM5 simulator system.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Remote Execution in Distributed Memory MPSoC.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010).
Int. J. Reconfig. Comp., 2011

PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
Embedded Systems Letters, 2011

Embedded MRAM for high-speed computing.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Evaluation of a distributed fault handler method for MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Modular Framework for Multi-level Multi-device MPSoC Simulation.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Design of MRAM based logic circuits and its applications.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Achieving composability in NoC-based MPSoCs through QoS management at software level.
Proceedings of the Design, Automation and Test in Europe, 2011

An Introduction to Multi-Core System on Chip - Trends and Challenges.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Computational Science, 2010

Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips.
J. Low Power Electronics, 2010

Run-time mapping for dynamic reconfiguration management in embedded systems.
IJES, 2010

Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories.
IET Computers & Digital Techniques, 2010

Adaptation Strategies in Multiprocessors System on Chip.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Evaluating the impact of task migration in multi-processor systems-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM).
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Flexible and distributed real-time control on a 4G telecom MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem.
Proceedings of the Design, Automation and Test in Europe, 2010

An in-memory monitoring database for self adaptive MP2SoCs.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

D-Scale: A Scalable System-Level Dependable Method for MPSoCs.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfig. Comp., 2009

Selected Papers from ReCoSoC 2008.
Int. J. Reconfig. Comp., 2009

An Adaptive Message Passing MPSoC Framework.
Int. J. Reconfig. Comp., 2009

Adaptive energy-aware latency-constrained DVFS policy for MPSoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Bio-inspired Systems: Self-adaptability from Chips to Sensor-network Architectures.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009

Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
Proceedings of the Design, Automation and Test in Europe, 2009

JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009

A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
The PERPLEXUS bio-inspired hardware platform: A flexible and modular approach.
KES Journal, 2008

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC.
Int. J. Reconfig. Comp., 2008

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays.
Int. J. Reconfig. Comp., 2008

Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

MPI-Based Adaptive Task Migration Support on the HS-Scale System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications.
Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008

Bio-inspiration helps computers: A new machine.
Proceedings of the FPL 2008, 2008

Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008

A non-volatile run-time FPGA using thermally assisted switching MRAMS.
Proceedings of the FPL 2008, 2008

Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories.
Proceedings of the 13th European Test Symposium, 2008

2007
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
CoRR, 2007

Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Architectural Issues in Homogeneous NoC-Based MPSoC.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Technological hybridization for efficient runtime reconfigurable FPGAs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Architecture for Highly Reliable Embedded Flash Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Evaluation of design for reliability techniques in embedded flash memories.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
How to Secure Embedded Programmable Gate Arrays?
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Remanent SRAM Structure for Runtime Reconfigurable FPGA.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Parallel and Secure Architecture for Asymmetric Cryptography.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

New non-volatile FPGA concept using Magnetic Tunneling Junction.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Securing embedded programmable gate arrays in secure circuits.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Leak Resistant Architecture Against Side Channel Attacks.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Magnetic tunnelling junction based FPGA.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Contextual Resources use: a Proof of Concept through the APACHES' Platform.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

PE-ICE: Parallelized Encryption and Integrity Checking Engine.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006

Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Technique et Science Informatiques, 2005

Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Current mask generation: a transistor level security against DPA attacks.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

A new hardware countermeasure for masking power signatures of crypto cores.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Non-volatile SRAM-FPGA based on magnetic tunnelling junction.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Dynamic hardware multiplexing for coarse grain reconfigurable architectures.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Hardware Engines for Bus Encryption: A Survey of Existing Techniques.
Proceedings of the 2005 Design, 2005

2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004

2003
Are coarse grain reconfigurable architectures suitable for cryptography?
Proceedings of the IFIP VLSI-SoC 2003, 2003

Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002

2001
A Dynamically Reconfigurable Architecture for Embedded Systems.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001

The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems.
Proceedings of the Field-Programmable Logic and Applications, 2001

1999
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
Proceedings of the VLSI: Systems on a Chip, 1999


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