Gilles Sassatelli
Orcid: 0000-0002-6396-286X
According to our database1,
Gilles Sassatelli
authored at least 158 papers
between 1999 and 2023.
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Bibliography
2023
Frontiers Comput. Neurosci., February, 2023
Sustain. Comput. Informatics Syst., January, 2023
Optimization of Data and Energy Migrations in Mini Data Centers for Carbon-Neutral Computing.
IEEE Trans. Sustain. Comput., 2023
2022
ACM Trans. Embed. Comput. Syst., 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
GANNoC: A Framework for Automatic Generation of NoC Topologies using Generative Adversarial Networks.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
2019
Microprocess. Microsystems, 2019
Empirical model-based performance prediction for application mapping on multicore architectures.
J. Syst. Archit., 2019
IET Comput. Digit. Tech., 2019
Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures.
CoRR, 2019
IEEE Access, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
2018
Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation.
Microprocess. Microsystems, 2018
J. Low Power Electron., 2018
Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Microprocess. Microsystems, 2017
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing.
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures.
IEEE Trans. Computers, 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures.
CoRR, 2016
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural Networks.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Design space exploration for complex automotive applications: an engine control system case study.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016
2015
A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embed. Comput. Syst., 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Trends on the application of emerging nonvolatile memory to processors and programmable devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Instruction-driven timing CPU model for efficient embedded software development using OVP.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
Int. J. Distributed Sens. Networks, 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2011
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010).
Int. J. Reconfigurable Comput., 2011
PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
IEEE Embed. Syst. Lett., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Achieving composability in NoC-based MPSoCs through QoS management at software level.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Comput. Sci., 2010
J. Low Power Electron., 2010
Int. J. Embed. Syst., 2010
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories.
IET Comput. Digit. Tech., 2010
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in Homogeneous MPSoC systems.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM).
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfigurable Comput., 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Bio-inspired Systems: Self-adaptability from Chips to Sensor-network Architectures.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the IEEE Congress on Evolutionary Computation, 2009
A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Int. J. Knowl. Based Intell. Eng. Syst., 2008
Int. J. Reconfigurable Comput., 2008
Int. J. Reconfigurable Comput., 2008
Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications.
Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008
Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008
Proceedings of the FPL 2008, 2008
Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories.
Proceedings of the 13th European Test Symposium, 2008
2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007
PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
How to Secure Embedded Programmable Gate Arrays?
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Remanent SRAM Structure for Runtime Reconfigurable FPGA.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
A Parallel and Secure Architecture for Asymmetric Cryptography.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
A new hardware countermeasure for masking power signatures of crypto cores.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Non-volatile SRAM-FPGA based on magnetic tunnelling junction.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the 2005 Design, 2005
2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004
2003
Are coarse grain reconfigurable architectures suitable for cryptography?
Proceedings of the IFIP VLSI-SoC 2003, 2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the Field-Programmable Logic and Applications, 2001
1999
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
Proceedings of the VLSI: Systems on a Chip, 1999