Luigi Carro

According to our database1, Luigi Carro authored at least 334 papers between 1993 and 2019.

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Bibliography

2019
Analyzing and Increasing the Reliability of Convolutional Neural Networks on GPUs.
IEEE Trans. Reliability, 2019

A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.
T. HiPEAC, 2019

A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Kernel and layer vulnerability factor to evaluate object detection reliability in GPUs.
IET Computers & Digital Techniques, 2019

Skipping CNN Convolutions Through Efficient Memoization.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Using Frame Similarity for Low Energy Software-Only IoT Video Recognition.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

RAW 2019 Keynote Speaker.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Detecting Errors in Convolutional Neural Networks Using Inter Frame Spatio-Temporal Correlation.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Impact of Reduced Precision in the Reliability of Deep Neural Networks for Object Detection.
Proceedings of the 24th IEEE European Test Symposium, 2019

TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Repair of FPGA-Based Real-Time Systems With Variable Slacks.
ACM Trans. Design Autom. Electr. Syst., 2018

Energy-Delay-FIT Product to compare processors and algorithm implementations.
Microelectronics Reliability, 2018

NFκB pathway analysis: An approach to analyze gene co-expression networks employing feedback cycles.
Computational Biology and Chemistry, 2018

Efficient Local Memory Support for Approximate Computing.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Exploring IoT platform with technologically agnostic processing-in-memory framework.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

HIPE: HMC instruction predication extension applied on database processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Processing in 3D memories to speed up operations on complex data structures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Employing classification-based algorithms for general-purpose approximate computing.
Proceedings of the 55th Annual Design Automation Conference, 2018

Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications.
Proceedings of the 55th Annual Design Automation Conference, 2018

Design space exploration for PIM architectures in 3D-stacked memories.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Exploring redundancy granularities to repair real-time FPGA-based systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Evaluation and Mitigation of Soft-Errors in Neural Network-Based Object Detection in Three GPU Architectures.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

Operand size reconfiguration for big data processing in memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An energy-efficient memory hierarchy for multi-issue processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

NIM: An HMC-Based Machine for Neuron Computation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.
Signal Processing Systems, 2016

Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication.
ACM Trans. Embedded Comput. Syst., 2016

Evaluation of Histogram of Oriented Gradients Soft Errors Criticality for Automotive Applications.
TACO, 2016

Improving performance in VLIW soft-core processors through software-controlled scratchpads.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

The Impact of Heterogeneity on a Reconfigurable Multicore System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Leveraging Compiler Support on VLIW Processors for Efficient Power Gating.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Scalable memory architecture for soft-core processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A reconfigurable heterogeneous multicore with a homogeneous ISA.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Large vector extensions inside the HMC.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

Low Cost Dynamic Scrubbing for Real-Time Systems.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Optimum design of a banked memory with power management for wireless sensor networks.
Wireless Networks, 2015

Fine-Grained Fast Field-Programmable Gate Array Scrubbing.
IEEE Trans. VLSI Syst., 2015

A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal.
TRETS, 2015

Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity.
IET Computers & Digital Techniques, 2015

A multiple-ISA reconfigurable architecture.
Design Autom. for Emb. Sys., 2015

Evaluation of energy savings on a VLIW processor through dynamic issue-width adaptation.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Reconfigurable Vector Extensions inside the DRAM.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Bit-Flip Aware Control-Flow Error Detection.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Opportunities and Challenges of Performing Vector Operations inside the DRAM.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture.
Proceedings of the 16th Latin-American Test Symposium, 2015

A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Performance evaluation of hierarchical NoC topologies for stacked 3D ICs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

HMC and DDR Performance Trade-offs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

The Path to Exascale: Code Optimizations and Hardening Solutions Reliability.
Proceedings of the 5th Workshop on Fault Tolerance for HPC at eXtreme Scale, 2015

Understanding GPU errors on large-scale HPC systems and the implications for system design and operation.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

A non-conservative software-based approach for detecting illegal CFEs caused by transient faults.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

NFRs early estimation through software metrics.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting cache conflicts to reduce radiation sensitivity of operating systems on embedded systems.
Proceedings of the 2015 International Conference on Compilers, 2015

Saving memory movements through vector processing in the DRAM.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems.
TRETS, 2014

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectronics Reliability, 2014

Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques.
Microelectronics Reliability, 2014

A transparent and adaptive reconfigurable system.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

GPUs Neutron Sensitivity Dependence on Data Type.
J. Electronic Testing, 2014

Early Estimation of NFRs for Embedded System Using Design Metrics.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

Towards a Dynamic and Reconfigurable Multicore Heterogeneous System.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

Hardware Virtualization on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

A run-time modulo scheduling by using a binary translation mechanism.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Adaptive multiple switching strategy toward an ideal NoC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Fault injection in GPGPU cores to validate and debug robust parallel applications.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

An adaptive low-power receiver architecture for IEEE 802.15.4 standard.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

Reducing embedded software radiation-induced failures through cache memories.
Proceedings of the 19th IEEE European Test Symposium, 2014

Impact of GPUs Parallelism Management on Safety-Critical and HPC Applications Reliability.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Radiation Sensitivity of High Performance Computing Applications on Kepler-Based GPGPUs.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

GPGPUs ECC efficiency and efficacy.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Reliable execution of statechart-generated correct embedded software under soft errors.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

GPGPUs: How to combine high computational power with high reliability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Towards Code Safety with High Performance.
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

2013
Multicore Systems on Chip.
, 2013

A NOC closed-loop performance monitor and adapter.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Towards a multiple-ISA embedded system.
Journal of Systems Architecture - Embedded Systems Design, 2013

Guest Editorial: Special Issue on 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI).
International Journal of Parallel Programming, 2013

Quality Impact on Software Performance.
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013

A Multiple-ISA Reconfigurable Architecture.
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013

A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Neutron sensitivity of integer and floating point operations executed in GPUs.
Proceedings of the 14th Latin American Test Workshop, 2013

A run-time adaptive multiprocessor system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Experimental evaluation of GPUs radiation sensitivity and algorithm-based fault tolerance efficiency.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Low-Power Processors Require Effective Memory Partitioning.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Compiler Optimizations Do Impact the Reliability of Control-Flow Radiation Hardened Embedded Software.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

On the evaluation of soft-errors detection techniques for GPGPUs.
Proceedings of the 8th International Design and Test Symposium, 2013

Neutron sensitivity and software hardening strategies for matrix multiplication and FFT on graphics processing units.
Proceedings of the 3rd Workshop on Fault-tolerance for HPC at extreme scale, 2013

Accelerated FPGA repair through shifted scrubbing.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Experimental evaluation of thread distribution effects on multiple output errors in GPUs.
Proceedings of the 18th IEEE European Test Symposium, 2013

A New Memory Banking System for Energy-Efficient Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2013

A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation.
Proceedings of the Design, Automation and Test in Europe, 2013

Scrubbing unit repositioning for fast error repair in FPGAs.
Proceedings of the International Conference on Compilers, 2013

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

Impact on Reliability in the Control-Flow of Programs under Compiler Optimizations.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Evaluating Dalvik Instructions through Dynamic Analysis of Bytecodes.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Adaptive parallelism exploitation under physical and real-time constraints for resilient systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Adapting communication for adaptable processors: A multi-axis reconfiguration approach.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Floorplan-aware hierarchical NoC topology with GALS interfaces.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Neutron radiation test of graphic processing units.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Fast error detection through efficient use of hardwired resources in FPGAs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Fault-Tolerant Algebraic Architecture for radiation induced soft-errors.
Proceedings of the 17th IEEE European Test Symposium, 2012

Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Fast single-FPGA fault injection platform.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Embedded reconfigurable architectures.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Reconfigurable Routers for Low Power and High Performance.
IEEE Trans. VLSI Syst., 2011

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfig. Comp., 2011

Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates.
Int. J. Reconfig. Comp., 2011

Two-levels of adaptive buffer for virtual channel router in NoCs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Performance Overhead from the Usage of Software Abstraction on Complex Embedded Systems.
Proceedings of the Brazilian Symposium on Computing System Engineering, 2011

AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

A reconfigurable fabric supporting full C/C++ input.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Mobile Agents Model and Performance Analysis of a Wireless Sensor Network Target Tracking Application.
Proceedings of the Smart Spaces and Next Generation Wired/Wireless Networking, 2011

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

Energy efficient pseudo-cache architecture through fine-grained reconfigurability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Matrix control-flow algorithm-based fault tolerance.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links.
Proceedings of the 16th European Test Symposium, 2011

An Area Effective Parity-Based Fault Detection Technique for FPGAs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011

An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture.
Proceedings of the 14th International Conference on Compilers, 2011

CReAMS: An Embedded Multiprocessor Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Towards an Adaptable Multiple-ISA Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Run-time resource instantiation for fault tolerance in FPGAs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A broad strategy to detect crosstalk faults in network-on-chip interconnects.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Monitor-adapter coupling for NOC performance tuning.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Special session on multicore architectures for embedded systems.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Voltage-mode quaternary FPGAs: An evaluation of interconnections.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A low-energy approach for context memory in reconfigurable systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Multiple Bit Error Detection and Correction in Memory.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

System Level Hardening by Computing with Matrices.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A New Soft-Error Resilient Voltage-Mode Quaternary Latch.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A new quaternary FPGA based on a voltage-mode multi-valued circuit.
Proceedings of the Design, Automation and Test in Europe, 2010

Challenges for embedded multicore architecture.
Proceedings of the 2010 International Conference on Compilers, 2010

Towards Estimating Physical Properties of Embedded Systems using Software Quality Metrics.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

Multi-core Systems on Chip.
Proceedings of the Handbook of Signal Processing Systems, 2010

Dynamic Reconfigurable Architectures and Transparent Optimization Techniques - Automatic Acceleration of Software Execution.
Springer, ISBN: 978-90-481-3912-5, 2010

2009
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs.
Microelectronics Journal, 2009

Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.
Integration, 2009

Resource-and-time-aware test strategy for configurable quaternary logic blocks.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Reliability aware yield improvement technique for nanotechnology based circuits.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Introduction to the Future of Reconfigurable Computing and Processor Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Adaptive router architecture based on traffic behavior observability.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

NoC Power Optimization Using a Reconfigurable Router.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Increasing memory yield in future technologies through innovative design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A low cost and adaptable routing network for reconfigurable systems.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Invariant checkers: An efficient low cost technique for run-time transient errors detection.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A fast error correction technique for matrix multiplication algorithms.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

The Case for Interpreted Languages in Sensor Networks.
Proceedings of the Analysis, 2009

New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies.
Proceedings of the Analysis, 2009

A new RC design for mixed-grain based dynamically reconfigurable architectures.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Dynamically Adapted Low Power ASIPs.
Proceedings of the Reconfigurable Computing: Architectures, 2009

The Need for Reconfigurable Routers in Networks-on-Chip.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Dynamically Adapted Low-Energy Fault Tolerant Processors.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electronic Testing, 2008

Majority Logic Mapping for Soft Error Dependability.
J. Electronic Testing, 2008

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

An efficient test and characterization approach for nanowire-based architectures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Software Quality Metrics and their Impact on Embedded Software.
Proceedings of the Model-based Methodologies for Pervasive and Embedded Software, 2008

Binary translation process to optimize nanowire arrays usage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Balancing reconfigurable data path resources according to application requirements.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

On the Use of Software Quality Metrics to Improve Physical Properties of Embedded Systems.
Proceedings of the Distributed Embedded Systems: Design, 2008

Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Proceedings of the FPL 2008, 2008

XOR-based Low Cost Checkers for Combinational Logic.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Using UML as Front-end for Heterogeneous Software Code Generation Strategies.
Proceedings of the Design, Automation and Test in Europe, 2008

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electronic Testing, 2007

Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals.
J. Electronic Testing, 2007

Reducing Test Time Using an Enhanced RF Loopback.
J. Electronic Testing, 2007

Crosstalk- and SEU-Aware Networks on Chips.
IEEE Design & Test of Computers, 2007

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.
Design Autom. for Emb. Sys., 2007

Noise Figure Evaluation Using Low Cost BIST
CoRR, 2007

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
CoRR, 2007

Distributed real-time embedded systems: Recent advances, future trends and their impact on manufacturing plant control.
Annual Reviews in Control, 2007

RF Digital Signal Generation Beyond Nyquist.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Transparent acceleration of data dependent instructions for general purpose processors.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Analysis of the use of declarative languages for enhanced embedded system software development.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Using majority logic to cope with long duration transient faults.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Object and method exploration for embedded systems applications.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Fitting the router characteristics in NoCs to meet QoS requirements.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A soft error robust and power aware memory design.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Object-Oriented Reconfiguration.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Using built-in sensors to cope with long duration transient faults in future technologies.
Proceedings of the 2007 IEEE International Test Conference, 2007

Transparent Dataflow Execution for Embedded Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Embedded SW Design Space Exploration and Automation using UML-Based Tools.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter.
Proceedings of the 12th European Test Symposium, 2007

Digital Generation of Signals for Low Cost RF BIST.
Proceedings of the 12th European Test Symposium, 2007

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies.
Proceedings of the 12th European Test Symposium, 2007

Spare Parts in Analog Circuits: A Filter Example.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A low-SER efficient core processor architecture for future technologies.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.
Proceedings of the 44th Design Automation Conference, 2007

2006
A low power high performance CMOS voltage-mode quaternary full adder.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A cell library for low power high performance CMOS voltage-mode quaternary logic.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Evaluation of SEU and crosstalk effects in network-on-chip switches.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Cache performance impacts for stack machines in embedded systems.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Advantages of Java Processors in Cache Performance and Power for Embedded Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Early Embedded Software Design Space Exploration Using UML-Based Estimation.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk.
Proceedings of the 2006 IEEE International Test Conference, 2006

Reconfigurable analog interface for mixed signal SOC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable communications for image processing applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Increasing analog programmability in SoCs.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Reconfiguration of embedded Java applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits.
Proceedings of the 11th European Test Symposium, 2006

SET Fault Tolerant Combinational Circuits Based on Majority Logic.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Online hardening of programs against SEUs and SETs.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

An improved RF loopback for test time reduction.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

The Molen FemtoJava Engine.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM.
RITA, 2005

Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging.
J. Low Power Electronics, 2005

Low Cost On-Line Testing Strategy for RF Circuits.
J. Electronic Testing, 2005

Low Cost BIST for Static and Dynamic Testing of ADCs.
J. Electronic Testing, 2005

Adding value to design and test through education: What are the challenges?
IEEE Design & Test of Computers, 2005

A constraint-based solution for on-line testing of processors embedded in real-time applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Making object oriented efficient for embedded system applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Going beyond TMR for protection against multiple faults.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Exploiting Java through binary translation for low power embedded reconfigurable systems.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Adaptive processing applied to the design of highly digital analog interfaces.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energy and latency evaluation of NoC topologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design space exploration on heterogeneous network-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Application of Binary Translation to Java Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Java Framework to Teach Computer Architecture.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

An Embedded SW Design Exploration Approach Based on UML Estimation Tools.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Object Orientation Problems When Applied to the Embedded Systems Domain.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Reliable Digital Circuits Design using Sigma-Delta Modulated Signals.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Noise Figure Evaluation Using Low Cost BIST.
Proceedings of the 2005 Design, 2005

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.
Proceedings of the 2005 Design, 2005

Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility.
Proceedings of the 42nd Design Automation Conference, 2005

Time and energy efficient mapping of embedded applications onto NoCs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Comparing high-level modeling approaches for embedded system design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Reusing an on-chip network for the test of core-based systems.
ACM Trans. Design Autom. Electr. Syst., 2004

INL and DNL estimation based on noise for ADC test.
IEEE Trans. Instrumentation and Measurement, 2004

Strategies for the integration of hardware and software IP components in embedded systems-on-chip.
Integration, 2004

A New FPGA for DSP Applications Integrating BIST Capabilities.
J. Electronic Testing, 2004

Searching for Global Test Costs Optimization in Core-Based Systems.
J. Electronic Testing, 2004

Designing Fault-Tolerant Techniques for SRAM-Based FPGAs.
IEEE Design & Test of Computers, 2004

Modeling and designing high performance analog reconfigurable circuits.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A VLIW low power Java processor for embedded applications.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications.
Proceedings of the Computer Systems: Architectures, 2004

A comparison of totally digital ADCs for SOCs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low Cost On-Line Testing of RF Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Design Space Exploration with Automatic Generation of IP-Based Embedded Software.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

The Implications of Real-Time Behavior in Networks-on-Chip Architectures.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

Evaluating High-Level Models for Real-Time Embedded Systems Design.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

Achieving wide frequency range in an analog FPGA.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A Low Power FPAA for Wide Band Applications.
Proceedings of the Field Programmable Logic and Application, 2004

Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach.
Proceedings of the Field Programmable Logic and Application, 2004

Towards a BIST technique for noise figure evaluation.
Proceedings of the 9th European Test Symposium, 2004

Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Arithmetic Operators Robust to Multiple Simultaneous Upsets.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Low Cost Analog Testing of RF Signal Paths.
Proceedings of the 2004 Design, 2004

Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs.
Proceedings of the 2004 Design, 2004

Designing and testing fault-tolerant techniques for SRAM-based FPGAs.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
A multiple bit upset tolerant SRAM memory.
ACM Trans. Design Autom. Electr. Syst., 2003

Testing analog circuits using spectral analysis.
Microelectronics Journal, 2003

A Statistical Sampler for a New On-Line Analog Test Method.
J. Electronic Testing, 2003

The SigmaDelta-BIST Method Applied to Analog Filters.
J. Electronic Testing, 2003

Circuit-Level Considerations for Mixed-Signal Programmable Components.
IEEE Design & Test of Computers, 2003

Ultra Low Cost Analog BIST Using Spectral Analysis.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

The Impact of NoC Reuse on the Testing of Core-based Systems.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An All-Digital ADC for Instrumentation within SOCs.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Low Power Java Processor for Embedded Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Testing RF Signal Paths Using Spectral Analysis and Subsampling.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A Universal High-Performance Analog Interface for Signal Processing SOCs.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Scheduling Policy Costs on a JAVA Microcontroller.
Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003

Power-aware NoC Reuse on the Testing of Core-based Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Efficient signal processing in embedded Java systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An analog signal interface with constant performance for SoCs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Exploiting reconfigurability for low-power control of embedded processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Reducing pin and area overhead in fault-tolerant FPGA-based designs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Ultimate low cost analog BIST.
Proceedings of the 40th Design Automation Conference, 2003

Designing fault tolerant systems into SRAM-based FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

2002
Efficient architecture for FPGA-based microcontrollers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Comparison of digital linearization methods for embedded sensor interfaces.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Statistical Sampler for a New On-line Analog Test Method.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Test Planning and Design Space Exploration in a Core-Based Environment.
Proceedings of the 2002 Design, 2002

2001
Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S.
RITA, 2001

Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.
J. Electronic Testing, 2001

Making Java Work for Microcontroller Applications.
IEEE Design & Test of Computers, 2001

Built-in Test of Analog Non-Linear Circuits in a SOC Environment.
Proceedings of the SOC Design Methodologies, 2001

2000
A new adaptive analog test and diagnosis system.
IEEE Trans. Instrumentation and Measurement, 2000

FPGA Architecture Comparison for Non-Conventional Signal Processing.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

A Design Methodology for Embedded Systems based on Multiple Processors.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

FPGA Based Systems with Linear and Non-Linear Signal Processing Capabilities.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

System Design Based on Single Language and Single-Chip Java ASIP Microcontroller.
Proceedings of the 2000 Design, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
Proceedings of the 2000 Design, 2000

Non-Linear Components for Mixed Circuits Analog Front-End.
Proceedings of the 2000 Design, 2000

System Synthesis for Multiprocessor Embedded Applications.
Proceedings of the 2000 Design, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Object-Oriented Modeling and Co-Simulation of Embedded Systems.
Proceedings of the VLSI: Systems on a Chip, 1999

Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999

Architecture Considerations for Mixed Signals FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.
Proceedings of the 1999 Design, 1999

1998
Efficient Analog Test Methodology Based on Adaptive Algorithms.
Proceedings of the 35th Conference on Design Automation, 1998

1997
F-Timer: dedicated FPGA to real-time systems design support.
Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, 1997

1996
Prototyping and reengineering of microcontroller-based systems.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Embedded Systems Design with Frontend Compilers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

System Design using ASIPs.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

1994
Algorithms and architectures to computational systems implementation.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

1993
SHC-SLX: A levelized compiled, event driven interpreted VLSI simulator.
Microprocessing and Microprogramming, 1993


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