Andrea Cappelli

Orcid: 0000-0003-1391-5202

According to our database1, Andrea Cappelli authored at least 16 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2023
A Survey on Recent Approaches to Question Difficulty Estimation from Text.
ACM Comput. Surv., 2023

2021
On the application of Transformers for estimating the difficulty of Multiple-Choice Questions from text.
Proceedings of the 16th Workshop on Innovative Use of NLP for Building Educational Applications, 2021

2020
R2DE: a NLP approach to estimating IRT parameters of newly generated questions.
Proceedings of the LAK '20: 10th International Conference on Learning Analytics and Knowledge, 2020

Introducing a Framework to Assess Newly Created Questions with Natural Language Processing.
Proceedings of the Artificial Intelligence in Education - 21st International Conference, 2020

2017
Conditional random fields with semantic enhancement for named-entity recognition.
Proceedings of the 7th International Conference on Web Intelligence, Mining and Semantics, 2017

Effects of Semantic Analysis on Named-Entity Recognition with Conditional Random Fields.
Proceedings of the 25th Italian Symposium on Advanced Database Systems, 2017

2013
Modeling the dynamic self-heating of PCM.
Proceedings of the European Solid-State Device Research Conference, 2013

2010
A-D-E Classification of Conformal Field Theories.
Scholarpedia, 2010

2006
Control architectures for reconfigurable digital systems.
PhD thesis, 2006

XiSystem: a XiRisc-based SoC with reconfigurable IO module.
IEEE J. Solid State Circuits, 2006

A Multi-Context Pipelined Array for Embedded Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
An Embedded Reconfigurable Datapath for SoC.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
A VLIW processor with reconfigurable instruction set for embedded applications.
IEEE J. Solid State Circuits, 2003

Decoder-Based Multi-Context Interconnect Architecture.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003


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