Fabio Campi

According to our database1, Fabio Campi authored at least 47 papers between 2003 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
Introducing IC reliability elements in digital circuits and systems design education.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Feasibility of Support Vector Machine gesture classification on a wearable embedded device.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

Design of digital modules for capacitive proximity sensing system applications.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
Design and Implementation of a Power-aware FFT Core for OFDM-based DSA-enabled Cognitive Radios.
J. Signal Process. Syst., 2015

2014
Approximate computing for complexity reduction in timing synchronization.
EURASIP J. Adv. Signal Process., 2014

Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Training communication skills in project-oriented microelectronics courses.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Accomodating the fast-paced evolution of VLSI in engineering curricula.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013

MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems.
ACM Trans. Embed. Comput. Syst., 2013

Design methodology for low-power embedded microprocessors.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Exploiting body biasing for leakage reduction: A case study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2011
The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform.
Int. J. Parallel Program., 2011

2010
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing.
IEEE J. Solid State Circuits, 2010

Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization.
J. Low Power Electron., 2010

Signal and power integrity for SoCs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A multi-core signal processor for heterogeneous reconfigurable computing.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A heterogeneous digital signal processor implementation for dynamically reconfigurable computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications.
J. Syst. Archit., 2008

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Des. Test Comput., 2008

Sustainable (re-) configurable solutions for the high volume SoC market.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reconfigurable hardware: The holy grail of matching performance with programming productivity.
Proceedings of the FPL 2008, 2008

Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array.
Proceedings of the Design, Automation and Test in Europe, 2008

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection.
Proceedings of the International Symposium on System-on-Chip, 2007

Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A dynamically adaptive DSP for heterogeneous reconfigurable platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A case-study on multimedia applications for the XiRisc reconfigurable processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A stream register file unit for reconfigurable processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design and implementation of a reconfigurable heterogeneous multiprocessor SoC.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A low-power system-on-chip for the documentation of road accidents.
IEEE Trans. Circuits Syst. Video Technol., 2005

A FPGA Implementation of An Open-Source Floating-Point Computation System.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

A reconfigurable FPU as IP component for SoCs.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Compact Buffered Routing Architecture.
Proceedings of the Field Programmable Logic and Application, 2004

Routing architecture for multi-context FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

A XiRisc-based SoC for embedded DSP applications.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and Actuators.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Decoder-Based Multi-Context Interconnect Architecture.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A C-based algorithm development flow for a reconfigurable processor architecture.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

A system level IP integration methodology for fast SOC design.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

A flexible LUT-based carry chain for FPGAs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A pipelined configurable gate array for embedded processors.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003


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