Luciano Lavagno

According to our database1, Luciano Lavagno authored at least 218 papers between 1990 and 2019.

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Bibliography

2019
Neural network-based indoor tag-less localization using capacitive sensors.
Proceedings of the 2019 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2019 ACM International Symposium on Wearable Computers, 2019

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Capacitive Sensor for Tagless Remote Human Identification Using Body Frequency Absorption Signatures.
IEEE Trans. Instrumentation and Measurement, 2018

Design space exploration of multi-core RTL via high level synthesis from OpenCL models.
Microprocess. Microsystems, 2018

Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Wireless Sensor Networks.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow.
Microprocess. Microsystems, 2017

Performance of Machine Learning Classifiers for Indoor Person Localization With Capacitive Sensors.
IEEE Access, 2017

High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?
IEEE Access, 2017

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis.
IEEE Access, 2017

Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis.
IEEE Access, 2017

High sensitivity, low noise front-end for long range capacitive sensors for tagless indoor human localization.
Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Long range, high sensitivity, low noise capacitive sensor for tagless indoor human localization.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

2016
Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis.
ACM Trans. Embedded Comput. Syst., 2016

Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project.
Sensors, 2016

A Tagless Indoor Localization System Based on Capacitive Sensing Technology.
Sensors, 2016

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL.
Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis.
Proceedings of the 2016 European Modelling Symposium, 2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications.
ACM Trans. Embedded Comput. Syst., 2015

Interactive Trace-Based Analysis Toolset for Manual Parallelization of C Programs.
ACM Trans. Embedded Comput. Syst., 2015

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits.
IEEE Trans. on Circuits and Systems, 2015

Routing-Aware Design of Indoor Wireless Sensor Networks Using an Interactive Tool.
IEEE Systems Journal, 2015

Analysis and Implementation of the Semi-Global Matching 3D Vision Algorithm Using Code Transformations and High-Level Synthesis.
Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

Low power methodology for an ASIC design flow based on high-level synthesis.
Proceedings of the 23rd International Conference on Software, 2015

Reactive clocks with variability-tracking jitter.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
A Model-Based Approach for Bridging Virtual and Physical Sensor Nodes in a Hybrid Simulation Framework.
Sensors, 2014

Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project.
Microprocess. Microsystems, 2014

Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.
J. Electronic Imaging, 2014

A Secure Online Key Establishment Scheme for Mobile Heterogeneous Sensor Networks.
IJDSN, 2014

Online Authentication and Key Establishment Scheme for Heterogeneous Sensor Networks.
IJDSN, 2014

Energy-aware parallelization flow and toolset for C code.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Metastability in Better-Than-Worst-Case Designs.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
HEAP: A Highly Efficient Adaptive multi-Processor framework.
Microprocess. Microsystems, 2013

Implementation and performance analysis of variable latency adders.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Design of a pseudo-log image transform IP in an HLS-based memory management framework.
Proceedings of the Real-Time Image and Video Processing 2013, 2013

A key management scheme for Content Centric Networking.
Proceedings of the 2013 IFIP/IEEE International Symposium on Integrated Network Management (IM 2013), 2013

Design space exploration and synthesis for digital signal processing algorithms from Simulink models.
Proceedings of the 8th International Design and Test Symposium, 2013

EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Share with care: a quantitative evaluation of sharing approaches in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
An Authentication and Key Establishment Scheme for the IP-Based Wireless Sensor Networks.
Proceedings of the 3rd International Conference on Ambient Systems, 2012

Selected Articles from the CDNLive! EMEA 2012 Conference.
J. Low Power Electronics, 2012

Dynamic Trace-Based Data Dependency Analysis for Parallelization of C Programs.
Proceedings of the 12th IEEE International Working Conference on Source Code Analysis and Manipulation, 2012

A Service-driven Development Tool for Wireless Sensor Network.
Proceedings of the PECCS 2012, 2012

A routing-algorithm-aware design tool for indoor wireless sensor networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Exploiting area/delay tradeoffs in high-level synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Designing parameterized signal processing ips for high level synthesis in a model based design environment.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Guest Editors' Introduction: Asynchronous Design Is Here to Stay (and Is More Mainstream Than You Thought).
IEEE Design & Test of Computers, 2011

Model-based rapid prototyping of multirate digital signal processing algorithms.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Realistic performance-constrained pipelining in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

An Energy and Memory-Efficient Key Management Scheme for Mobile Heterogeneous Sensor Networks.
Proceedings of the CRiSIS 2011, 2011

An extended framework for WSN applications.
Proceedings of the Consumer Communications and Networking Conference, 2011

Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques.
ACM Trans. Design Autom. Electr. Syst., 2010

Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization.
J. Low Power Electronics, 2010

Hy-Sim: model based hybrid simulation framework for WSN application development.
Proceedings of the 3rd International Conference on Simulation Tools and Techniques, 2010

HILAC: A framework for Hardware In the Loop simulation and multi-platform Automatic Code Generation of WSN Applications.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

MEOW: Model-based design of an energy-optimized protocol stack for wireless sensor networks.
Proceedings of the 35th Annual IEEE Conference on Local Computer Networks, 2010

Energy optimization framework for WSN design.
Proceedings of the 9th International Conference on Information Processing in Sensor Networks, 2010

An extended framework for the development of WSN applications.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2010

Energy optimization at the MAC layer for a forest fire monitoring wireless sensor network.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

Energy and throughput optimization of a Zigbee-compatible MAC protocol for wireless sensor networks.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

Incremental high-level synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A comparison of software platforms for wireless sensor networks: MANTIS, TinyOS, and ZigBee.
ACM Trans. Embedded Comput. Syst., 2009

An Efficient Data Aggregation Algorithm for Cluster-based Sensor Network.
JNW, 2009

Enabling adaptability through elastic clocks.
Proceedings of the 46th Design Automation Conference, 2009

Design of Embedded Systems.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
A Framework for Modeling, Simulation and Automatic Code Generation of Sensor Network Application.
Proceedings of the Fifth Annual IEEE Communications Society Conference on Sensor, 2008

An Algorithm for Selecting the Cluster Leader in a Partially Connected Sensor Network.
Proceedings of the 3rd International Conference on Systems and Networks Communications, 2008

Porting application between wireless sensor network software platforms: TinyOS, MANTIS and ZigBee.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

A Symbolic Algorithm for the Synthesis of Bounded Petri Nets.
Proceedings of the Applications and Theory of Petri Nets, 29th International Conference, 2008

2007
Design Automation of Real-Life Asynchronous Devices and Systems.
Foundations and Trends in Electronic Design Automation, 2007

E2RINA: an Energy Efficient and Reliable In-Network Aggregation for Clustered Wireless Sensor Networks.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

A Fully-Automated Desynchronization Flow for Synchronous Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

An ultra-low energy asynchronous processor for Wireless Sensor Networks.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Quasi-Static Scheduling of Concurrent Specifications.
Proceedings of the Embedded Systems Handbook., 2005

Design of Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Guidelines for a graduate curriculum on embedded software and systems.
ACM Trans. Embedded Comput. Syst., 2005

Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Quasi-static scheduling of independent tasks for reactive systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A BMC-based formulation for the scheduling problem of hardware systems.
STTT, 2005

Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems.
IEEE Design & Test of Computers, 2005

A Time Slice Based Scheduler Model for System Level Design.
Proceedings of the 2005 Design, 2005

Design of Embedded Systems.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Designing an asynchronous microcontroller using Pipefitter.
IEEE Trans. VLSI Syst., 2004

Quasi-static Scheduling for Concurrent Architectures.
Fundam. Inform., 2004

DAC Highlights.
IEEE Design & Test of Computers, 2004

SoftContract: Model-Based Design of Error-Checking Code and Property Monitors.
Proceedings of the UML Modeling Languages and Applications, 2004

Coping with The Variability of Combinational Logic Delays.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform.
Proceedings of the 2004 Design, 2004

From Synchronous to Asynchronous: An Automatic Approach.
Proceedings of the 2004 Design, 2004

SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract.
Proceedings of the 2004 Design, 2004

Handshake Protocols for De-Synchronization.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Guest Editors' Introduction: Trends and Directions in Microelectronics.
IEEE Micro, 2003

A BMC-formulation for the scheduling problem in highly constrained hardware Systems.
Electron. Notes Theor. Comput. Sci., 2003

DAC Highlights.
IEEE Design & Test of Computers, 2003

Metropolis: An Integrated Electronic System Design Environment.
IEEE Computer, 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform.
Proceedings of the 2003 Design, 2003

Hardware/Software Design Space Exploration for a Reconfigurable Processor.
Proceedings of the 2003 Design, 2003

Quasi-Static Scheduling for Concurrent Architectures.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

UML and Platform-based Design.
Proceedings of the UML for Real - Design of Embedded Real-Time Systems, 2003

2002
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. VLSI Syst., 2002

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Guest Editor?s Introduction: Systems on a Chip--The Next Electronic Frontier.
IEEE Micro, 2002

Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference.
IEEE Design & Test of Computers, 2002

Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Symbolic Approach for the Combined Solution of Scheduling and Allocation.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Automotive Virtual Integration Platforms: Why's, What's, and How's.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Models of IP's for Automotive Virtual Integration Platforms.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis.
Proceedings of the Embedded Software, Second International Conference, 2002

False Path Elimination in Quasi-Static Scheduling.
Proceedings of the 2002 Design, 2002

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems.
Proceedings of the Applications and Theory of Petri Nets 2002, 2002

Modeling and Designing Heterogeneous Systems.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001
Synchronous approach to the functional equivalence of embeddedsystem implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Constraints specification at higher levels of abstraction.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Generation of minimal size code for scheduling graphs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM.
Proceedings of the 38th Design Automation Conference, 2001

Embedded UML: a merger of real-time UML and co-design.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

High-level architectural co-simulation using Esterel and C.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

A software development tool chain for a reconfigurable processor.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Simulink-Based HW/SW Codesign of Embedded Neuro-Fuzzy Systems.
Int. J. Neural Syst., 2000

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.
Formal Methods in System Design, 2000

Formal Models for Embedded System Design.
IEEE Design & Test of Computers, 2000

Early Power Estimation for System-on-Chip Designs.
Proceedings of the Integrated Circuit Design, 2000

Compilation-based software performance estimation for system level design.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Behavioral-level test vector generation for system-on-chip designs.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

A Simulink(c)-Based Approach to System Level Design and Architecture Selection.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Evaluating System Dependability in a Co-Design Framework.
Proceedings of the 2000 Design, 2000

Efficient Power Co-Estimation Techniques for System-on-Chip Design.
Proceedings of the 2000 Design, 2000

Free MDD-Based Software Optimization Techniques for Embedded Systems.
Proceedings of the 2000 Design, 2000

Efficient methods for embedded system design space exploration.
Proceedings of the 37th Conference on Design Automation, 2000

Task generation and compile-time scheduling for mixed data-control embedded software.
Proceedings of the 37th Conference on Design Automation, 2000

Formal Models for Communication-Based Design.
Proceedings of the CONCUR 2000, 2000

Automatic test bench generation for simulation-based validation.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Software performance estimation strategies in a system-level design tool.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Hardware and Petri Nets: Application to Asynchronous Circuit Design.
Proceedings of the Application and Theory of Petri Nets 2000, 2000

1999
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Synthesis of software programs for embedded control applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

CAD Techniques for Embedded System Design.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

What is the cost of delay insensitivity?
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Fast Hardware-Software Co-simulation Using VHDL Models.
Proceedings of the 1999 Design, 1999

Synthesis of Embedded Software Using Free-Choice Petri Nets.
Proceedings of the 36th Conference on Design Automation, 1999

ECL: A Specification Environment for System-Level Design.
Proceedings of the 36th Conference on Design Automation, 1999

Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.
Proceedings of the 36th Conference on Design Automation, 1999

Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets.
Proceedings of the Application and Theory of Petri Nets 1999, 1999

1998
Modeling reactive systems in Java.
ACM Trans. Design Autom. Electr. Syst., 1998

Partial-scan delay fault testing of asynchronous circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Deriving Petri Nets for Finite Transition Systems.
IEEE Trans. Computers, 1998

The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems.
Journal of Circuits, Systems, and Computers, 1998

Scheduling for Embedded Real-Time Systems.
IEEE Design & Test of Computers, 1998

Rapid-Prototyping of Embedded Systems via Reprogrammable Devices.
Design Autom. for Emb. Sys., 1998

Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Lazy transition systems: application to timing optimization of asynchronous circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Interface synthesis: a vertical slice from digital logic to software components.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Don't Care-Based BDD Minimization for Embedded Software.
Proceedings of the 35th Conference on Design Automation, 1998

A Case Study in Embedded System Design: An Engine Control Unit.
Proceedings of the 35th Conference on Design Automation, 1998

A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

System-Level Design Models and Implementation Techniques.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997
A region-based theory for state assignment in speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

DAC 97 Panel: Next-Generation HDLs.
IEEE Design & Test of Computers, 1997

Asynchronous Implementation of Synchronous Esterel Specifications.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.
Proceedings of the European Design and Test Conference, 1997

Verification and synthesis of counters based on symbolic techniques.
Proceedings of the European Design and Test Conference, 1997

Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis.
Proceedings of the 34st Conference on Design Automation, 1997

Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

Automatic Generation of a Real-Time Operating System for Embedded Systems.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Partial order based approach to synthesis of speed-independent circuits.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Trade-off evaluation in embedded system design via co-simulation.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Coupling Asynchrony and Interrupts: Place Chart Nets.
Proceedings of the Application and Theory of Petri Nets 1997, 1997

1996
A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis.
Formal Methods in System Design, 1996

On the Models for Asynchronous Circuit Behaviour with OR Causality.
Formal Methods in System Design, 1996

A case study in computer-aided co-design of embedded controllers.
Design Autom. for Emb. Sys., 1996

Rapid-Prototyping of Embedded Systems via Reprogrammable Devices.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Design and Implementation of the Control Structure of the PAPRICA-3 Processor.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

Enhancing FSM Traversal by Temporary Re-Encoding.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Compact and complete test set generation for multiple stuck-faults.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Incremental re-encoding for symbolic traversal of product machines.
Proceedings of the conference on European design automation, 1996

Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.
Proceedings of the 33st Conference on Design Automation, 1996

Formal Verification of Embedded Systems based on CFSM Networks.
Proceedings of the 33st Conference on Design Automation, 1996

Complete state encoding based on the theory of regions.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Synthesis of hazard-free asynchronous circuits with bounded wire delays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Synthesis for testability techniques for asynchronous circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

High-Level Modeling and Design of Asynchronous Interface Logic.
IEEE Design & Test of Computers, 1995

Synthesizing Petri nets from state-based models.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool.
Proceedings of the 32st Conference on Design Automation, 1995

Synthesis of Software Programs for Embedded Control Applications.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Linear programming for hazard elimination in asynchronous circuits.
VLSI Signal Processing, 1994

A low latency asynchronous arbitration circuit.
IEEE Trans. VLSI Syst., 1994

Hardware-software codesign of embedded systems.
IEEE Micro, 1994

PAPRICA-3: A Real-Time Morhphological Image Processor.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

Testing redundant asynchronous circuits by variable phase splitting.
Proceedings of the Proceedings EURO-DAC'94, 1994

A case study in computer-aided codesign of embedded controllers.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Designing asynchronous circuits from behavioural specifications with internal conflicts.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

OR Causality: Modelling and Hardware Implementation.
Proceedings of the Application and Theory of Petri Nets 1994, 1994

1993
Automated synthesis of asynchronous interface circuits.
Microprocess. Microsystems, 1993

1992
Symbolic minimization of multilevel logic and the input encoding problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Solving the State Assignment Problem for Signal Transition Graphs.
Proceedings of the 29th Design Automation Conference, 1992

1991
Algorithms for Synthesis of Hazard-Free Asynchronous Circuits.
Proceedings of the 28th Design Automation Conference, 1991

1990
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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