Roberto Guerrieri

Affiliations:
  • University of Bologna, Italy


According to our database1, Roberto Guerrieri authored at least 87 papers between 1987 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Creamino: A Cost-Effective, Open-Source EEG-Based BCI System.
IEEE Trans. Biomed. Eng., 2019

2017
Parametric Detection and Classification of Compact Conductivity Contrasts With Electrical Impedance Tomography.
IEEE Trans. Instrum. Meas., 2017

2016
Parallel Solver for Diffuse Optical Tomography on Realistic Head Models With Scattering and Clear Regions.
IEEE Trans. Biomed. Eng., 2016

A Driving Right Leg Circuit (DgRL) for Improved Common Mode Rejection in Bio-Potential Acquisition Systems.
IEEE Trans. Biomed. Circuits Syst., 2016

2015
Power-Aware Job Scheduling on Heterogeneous Multicore Architectures.
IEEE Trans. Parallel Distributed Syst., 2015

Active Electrode IC for EEG and Electrical Impedance Tomography With Continuous Monitoring of Contact Impedance.
IEEE Trans. Biomed. Circuits Syst., 2015

EEG acquisition system based on active electrodes with common-mode interference suppression by Driving Right Leg circuit.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2014
Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Triangular Matrix Inversion on Heterogeneous Multicore Systems.
IEEE Trans. Parallel Distributed Syst., 2012

A Four-Shell Diffusion Phantom of the Head for Electrical Impedance Tomography.
IEEE Trans. Biomed. Eng., 2012

EIT Forward Problem Parallel Simulation Environment with Anisotropic Tissue and Realistic Electrode Models.
IEEE Trans. Biomed. Eng., 2012

Tuning solution of large non-Hermitian linear systems on multiple graphics processing unit accelerated workstations.
Int. J. High Perform. Comput. Appl., 2012

2011
Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling.
IEEE J. Solid State Circuits, 2011

Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wire.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing.
IEEE J. Solid State Circuits, 2010

Characterization of chip-to-chip wireless interconnections based on capacitive coupling.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

3D system on chip memory interface based on modeled capacitive coupling interconnections.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Triangular matrix inversion on Graphics Processing Unit.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Chip-to-chip communication based on capacitive coupling.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities.
IEEE J. Solid State Circuits, 2008

2007
3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly.
IEEE J. Solid State Circuits, 2007

Lab on a Chip for Live-Cell Manipulation.
IEEE Des. Test Comput., 2007

Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy?
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

3D Capacitive Interconnections for High Speed Interchip Communication.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Low leakage techniques for FPGAs.
IEEE J. Solid State Circuits, 2006

XiSystem: a XiRisc-based SoC with reconfigurable IO module.
IEEE J. Solid State Circuits, 2006

Yield prediction for 3D capacitive interconnections.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Design and implementation of a reconfigurable heterogeneous multiprocessor SoC.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Measuring Skin Topographic Structures through Capacitance Image Analysis.
Proceedings of the Advanced Video and Signal Based Surveillance, 2006

2005
A low-power system-on-chip for the documentation of road accidents.
IEEE Trans. Circuits Syst. Video Technol., 2005

In Vivo Quantitative Evaluation of Skin Ageing by Capacitance Image Analysis.
Proceedings of the 7th IEEE Workshop on Applications of Computer Vision / IEEE Workshop on Motion and Video Computing (WACV/MOTION 2005), 2005

Beyond the microscope: embedded detectors for cell biology applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low leakage design of LUT-based FPGAs.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Electrical measurement of alignment for 3D stacked chips.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

New Perspectives and Opportunities From the Wild West of Microelectronic Biochips.
Proceedings of the 2005 Design, 2005

A 0.14mW/Gbps high-density capacitive interface for 3D system integration.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Studying skin ageing through wavelet-based analysis of capacitive images.
Proceedings of the Advanced Video and Signal Based Surveillance, 2005

2004
A XiRisc-based SoC for embedded DSP applications.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A dynamically reconfigurable monolithic CMOS pressure sensor for smart fabric.
IEEE J. Solid State Circuits, 2003

A CMOS chip for individual cell manipulation and detection.
IEEE J. Solid State Circuits, 2003

A VLIW processor with reconfigurable instruction set for embedded applications.
IEEE J. Solid State Circuits, 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Word endpoints detection in the presence of non-stationary noise.
Proceedings of the 7th International Conference on Spoken Language Processing, ICSLP2002, 2002

Very low complexity prompted speaker verification system based on HMM-modeling.
Proceedings of the IEEE International Conference on Acoustics, 2002

2001
Low power techniques for flash memories.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A system-on-chip for pressure-sensitive fabric.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A complete system for NN classification based on a VLSI array processor.
Pattern Recognit., 2000

A low-power system-on-chip for the documentation of road accidents.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
A CMOS-only micro touch pointer.
IEEE J. Solid State Circuits, 1999

1998
A Geometric Approach to Maximum-Speed n-Dimensional Continuous Linear Interpolation in Rectangular Grids.
IEEE Trans. Computers, 1998

A fingerprint sensor based on the feedback capacitive sensing scheme.
IEEE J. Solid State Circuits, 1998

A low-power integrated circuit for remote speech recognition.
IEEE J. Solid State Circuits, 1998

A low-power, voice-controlled, H.263 video decoder for portable applications.
IEEE J. Solid State Circuits, 1998

OMI-Compliant Model for Virtual Emulation.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A 35 μW 1.1 V gate array 8×8 IDCT processor for video-telephony.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

A low-power VLSI feature extractor for speech recognition.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

A 1 V, 25 μW speech recognizer for portable systems.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Fuzzy-controlled perceptual coding of videophone sequences.
IEEE Trans. Fuzzy Syst., 1997

Fast board-level prototyping of a speech recognition system using virtual emulation.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

1996
Highly constrained neural networks for industrial quality control.
IEEE Trans. Neural Networks, 1996

A photodiode cell for applications to position and motion estimation sensors.
IEEE Trans. Ind. Electron., 1996

Automatic synthesis of analog fuzzy controllers: a hardware and software approach.
IEEE Trans. Ind. Electron., 1996

Fuzzy sets of rules for system identification.
IEEE Trans. Fuzzy Syst., 1996

A silicon compiler of analog fuzzy controllers: from behavioral specifications to layout.
IEEE Trans. Fuzzy Syst., 1996

An ASIC chip set for parallel fuzzy database mining.
IEEE Micro, 1996

A smoothly upgradable approach to virtual emulation of HW/SW systems.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

A VLSI array processor accelerator for k-NN classification.
Proceedings of the 13th International Conference on Pattern Recognition, 1996

Extraction of LP-based features from one-bit quantized speech signals for recognition purposes.
Proceedings of the 8th European Signal Processing Conference, 1996

1995
An enhanced two-level Boolean synthesis methodology for fuzzy rules minimization.
IEEE Trans. Fuzzy Syst., 1995

Massively parallel electromagnetic simulation for photolithographic applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Massively-parallel handwritten character recognition based on the distance transform.
Pattern Recognit., 1995

Adaptive Voting Rules for <i>k</i>-Nearest Neighbors Classifiers.
Neural Comput., 1995

A 2D-DCT low-power architecture for H.261 coders.
Proceedings of the 1995 International Conference on Acoustics, 1995

1993
Highly-constrained neural networks with application to visual inspection of machined parts.
Proceedings of the IEEE International Conference on Acoustics, 1993

An array-processor based architecture for classification problems.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
A novel metric for nearest-neighbor classification of hand-written digits.
Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

1991
A massively parallel algorithm for three-dimensional device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Massively parallel algorithms for scattering in optical lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1988
Three-dimensional capacitance evaluation on a Connection Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A new discretization strategy of the semiconductor equations comprising momentum and energy balance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
Sensitivity Analysis for Device Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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