Antonio Deledda

According to our database1, Antonio Deledda authored at least 12 papers between 2005 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A multi-core signal processor for heterogeneous reconfigurable computing.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A heterogeneous digital signal processor implementation for dynamically reconfigurable computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Des. Test Comput., 2008

Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array.
Proceedings of the Design, Automation and Test in Europe, 2008

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection.
Proceedings of the International Symposium on System-on-Chip, 2007

A dynamically adaptive DSP for heterogeneous reconfigurable platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
XiSystem: a XiRisc-based SoC with reconfigurable IO module.
IEEE J. Solid State Circuits, 2006

A stream register file unit for reconfigurable processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design and implementation of a reconfigurable heterogeneous multiprocessor SoC.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005


  Loading...