Andrew Laffely

According to our database1, Andrew Laffely authored at least 6 papers between 2003 and 2004.

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Bibliography

2004
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.
J. VLSI Signal Process., 2004

An architecture and compiler for scalable on-chip communication.
IEEE Trans. Very Large Scale Integr. Syst., 2004

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003
Using System On-A-Chip As A Vehicle For VLSI Design Education.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Targeting Tiled Architectures in Design Exploration.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.
Proceedings of the 2003 International Conference on Image Processing, 2003


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