Guy Gogniat

According to our database1, Guy Gogniat authored at least 123 papers between 1996 and 2020.

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Bibliography

2020
FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks.
J. Syst. Archit., 2020

Meet the Sherlock Holmes' of Side Channel Leakage: A Survey of Cache SCA Detection Techniques.
IEEE Access, 2020

2019
MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Sherlock Holmes of Cache Side-Channel Attacks in Intel's x86 Architecture.
Proceedings of the 7th IEEE Conference on Communications and Network Security, 2019

2018
Application Deployment Strategies for Spatial Isolation on Many-Core Accelerators.
ACM Trans. Embedded Comput. Syst., 2018

Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.
IEEE Trans. Computers, 2018

A small and adaptive coprocessor for information flow tracking in ARM SoCs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Run-time Detection of Prime + Probe Side-Channel Attack on AES Encryption Algorithm.
Proceedings of the 2018 Global Information Infrastructure and Networking Symposium, 2018

A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
The First 25 Years of the FPL Conference: Significant Papers.
ACM Trans. Reconfigurable Technol. Syst., 2017

A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm.
ACM Trans. Embedded Comput. Syst., 2017

Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs.
Microprocess. Microsystems, 2017

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Signal Process., 2017

ARMHEx: A framework for efficient DIFT in real-world SoCs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

ARMHEx: A hardware extension for DIFT on ARM-based SoCs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Somewhat/Fully Homomorphic Encryption: Implementation Progresses and Challenges.
Proceedings of the Codes, Cryptology and Information Security, 2017

2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls.
Microprocess. Microsystems, 2016

MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Towards risk aware NoCs for data protection in MPSoCs.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Dynamic spatially isolated secure zones for NoC-based many-core accelerators.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

ALMOS Many-Core Operating System Extension with New Secure-Enable Mechanisms for Dynamic Creation of Secure Zones.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

A Fast Evaluation Approach of Data Consistency Protocols within a Compilation Toolchain.
Proceedings of the International Conference on Computational Science 2016, 2016

Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Towards a hardware-assisted information flow tracking ecosystem for ARM processors.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., 2015

Disposable configuration of remotely reconfigurable systems.
Microprocess. Microsystems, 2015

NoC-Based Protection for SoC Time-Driven Attacks.
Embedded Systems Letters, 2015

Reconfigurable Group-Wise Security Architecture for NoC-Based MPSoCs Protection.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Efficient and flexible NoC-based group communication for secure MPSoCs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Exploration of polynomial multiplication algorithms for homomorphic encryption schemes.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

TSV protection: Towards secure 3D-MPSoC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Cycle-based Model to Evaluate Consistency Protocols within a Multi-protocol Compilation Tool-chain.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015

2014
Introduction to the Special Issue on the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12).
ACM Trans. Reconfigurable Technol. Syst., 2014

Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling.
ACM Trans. Reconfigurable Technol. Syst., 2014

3D-LeukoNoC: A dynamic NoC protection.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Using the Spring Physical Model to Extend a Cooperative Caching Protocol for Many-Core Processors.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Elastic security zones for NoC-based 3D-MPSoCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Configurable memory security in embedded systems.
ACM Trans. Embedded Comput. Syst., 2013

Recent Advances in Homomorphic Encryption: A Possible Future for Signal Processing in the Encrypted Domain.
IEEE Signal Process. Mag., 2013

Architectures of flexible symmetric key crypto engines - a survey: From hardware coprocessor to multi-crypto-processor system on chip.
ACM Comput. Surv., 2013

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Towards Practical Program Execution over Fully Homomorphic Encryption Schemes.
Proceedings of the Eighth International Conference on P2P, 2013

2012
Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance.
ACM Trans. Reconfigurable Technol. Syst., 2012

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection.
Int. J. Reconfigurable Comput., 2012

Hybrid-on-chip communication architecture for dynamic MP-SoC protection.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Designing formal reconfiguration control using UML/MARTE.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

Modeling and synthesis of a Dynamic and Partial Reconfiguration controller.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Lightweight reconfiguration security services for AXI-based MPSoCs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Closed-loop-based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study.
ACM Trans. Embedded Comput. Syst., 2011

Dynamic NoC-based architecture for MPSoC security implementation.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Asymmetric cache coherency: Improving multicore performance for non-uniform workloads.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Distributed Security for Communications and Memories in a Multiprocessor Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Efficient key-dependent message authentication in reconfigurable hardware.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation.
Proceedings of the Design, Automation and Test in Europe, 2011

Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Modeling and Formal Control of Partial Dynamic Reconfiguration.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Predictibility of inter-component latency in a software communications architecture operating environment.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

XPSoC: A reconfigurable solution for multimedia contents protection.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Rapid Application Development on Multi-processor Reconfigurable Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

UML design for dynamically reconfigurable multiprocessor embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A security approach for off-chip memory in embedded microprocessor systems.
Microprocess. Microsystems, 2009

Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A co-design approach for embedded system modeling and code generation with UML and MARTE.
Proceedings of the Design, Automation and Test in Europe, 2009

Ultra-Fast Downloading of Partial Bitstreams through Ethernet.
Proceedings of the Architecture of Computing Systems, 2009

2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Design and Architectures for Signal and Image Processing.
EURASIP J. Embed. Syst., 2008

A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Embed. Syst., 2008

System Level Design Space Exploration for Multiprocessor System on Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

Memory security management for reconfigurable embedded systems.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A Networked, Lightweight and Partially Reconfigurable Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Communication-Oriented Design Space Exploration for Reconfigurable Architectures.
EURASIP J. Embed. Syst., 2007

A Code Compression Method to Cope with Security Hardware Overheads.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

NOC-centric Security of Reconfigurable SoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A Code Compression Method with Confidentiality and Integrity Checking.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006
Exploration de l'espace de conception des architectures reconfigurables.
Technique et Science Informatiques, 2006

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

EPICURE: A partitioning and co-design framework for reconfigurable computing.
Microprocess. Microsystems, 2006

Dynamically configurable security for SRAM FPGA bitstreams.
IJES, 2006

System Level Design with UML: a Unified Approach.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Secure Architecture in Embedded Systems: an Overview.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Trusted computing - A new challenge for embedded systems.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Reconfigurable Security Support for Embedded Systems.
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

2005
Configurable Computing for High-Security/High-Performance Ambient Systems.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Reconfigurable Security Primitive for Embedded Systems.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Generic Design Space Exploration for Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2003
Interface design approach for system on chip based on configuration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Fast prototyping of reconfigurable architectures from a C program.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Targeting Tiled Architectures in Design Exploration.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Communication Costs Driven Design Space Exploration for Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

An estimation and exploration methodology from system-level specifications: application to FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Fast Design Space Exploration Method for Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2000
A codesign back-end approach for embedded system design.
ACM Trans. Design Autom. Electr. Syst., 2000

1998
Communication synthesis and HW/SW integration for embedded system design.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

A path analysis based partitioning for time constrained embedded systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
A codesign experiment in acoustic echo cancellation GMDF.
ACM Trans. Design Autom. Electr. Syst., 1997

A generic multi-unit architecture for codesign methodologies.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
A Codesign Experiment in Acoustic Echo Cancellation: GMDFa.
Proceedings of the 9th International Symposium on System Synthesis, 1996


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