Guy Gogniat
Orcid: 0000-0002-9528-5277
According to our database1,
Guy Gogniat
authored at least 141 papers
between 1996 and 2023.
Collaborative distances:
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Bibliography
2023
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures.
CoRR, 2023
Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections.
Proceedings of the IEEE European Symposium on Security and Privacy, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
The Kingsguard OS-level mitigation against cache side-channel attacks using runtime detection.
Ann. des Télécommunications, 2022
Novel Design for IE-Cache to Mitigate Conflict-based Cache-side Channel Attacks with Reduced Energy Consumption.
Proceedings of the 19th International Conference on Security and Cryptography, 2022
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Token-based authentication and access delegation for HW-accelerated telco cloud solution.
Proceedings of the 11th IEEE International Conference on Cloud Networking, 2022
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud.
Behavioral Synthesis for Hardware Security, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Proceedings of the UCC '21: 2021 IEEE/ACM 14th International Conference on Utility and Cloud Computing, Leicester, United Kingdom, December 6 - 9, 2021, 2021
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks.
J. Syst. Archit., 2020
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA.
Inf. Syst., 2020
Meet the Sherlock Holmes' of Side Channel Leakage: A Survey of Cache SCA Detection Techniques.
IEEE Access, 2020
IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction.
Proceedings of the ICT Systems Security and Privacy Protection, 2020
Proceedings of the Algorithms and Architectures for Parallel Processing, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 7th IEEE Conference on Communications and Network Security, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.
IEEE Trans. Computers, 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 Global Information Infrastructure and Networking Symposium, 2018
A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
ACM Trans. Reconfigurable Technol. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs.
Microprocess. Microsystems, 2017
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Signal Process., 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the Codes, Cryptology and Information Security, 2017
2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls.
Microprocess. Microsystems, 2016
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
ALMOS Many-Core Operating System Extension with New Secure-Enable Mechanisms for Dynamic Creation of Secure Zones.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
A Fast Evaluation Approach of Data Consistency Protocols within a Compilation Toolchain.
Proceedings of the International Conference on Computational Science 2016, 2016
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., 2015
Microprocess. Microsystems, 2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Exploration of polynomial multiplication algorithms for homomorphic encryption schemes.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Cycle-based Model to Evaluate Consistency Protocols within a Multi-protocol Compilation Tool-chain.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015
2014
Introduction to the Special Issue on the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12).
ACM Trans. Reconfigurable Technol. Syst., 2014
Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling.
ACM Trans. Reconfigurable Technol. Syst., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Using the Spring Physical Model to Extend a Cooperative Caching Protocol for Many-Core Processors.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
Recent Advances in Homomorphic Encryption: A Possible Future for Signal Processing in the Encrypted Domain.
IEEE Signal Process. Mag., 2013
Architectures of flexible symmetric key crypto engines - a survey: From hardware coprocessor to multi-crypto-processor system on chip.
ACM Comput. Surv., 2013
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Eighth International Conference on P2P, 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
Int. J. Reconfigurable Comput., 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2011
Closed-loop-based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study.
ACM Trans. Embed. Comput. Syst., 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Asymmetric cache coherency: Improving multicore performance for non-uniform workloads.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Distributed Security for Communications and Memories in a Multiprocessor Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation.
Proceedings of the Design, Automation and Test in Europe, 2011
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Predictibility of inter-component latency in a software communications architecture operating environment.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Microprocess. Microsystems, 2009
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
A co-design approach for embedded system modeling and code generation with UML and MARTE.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Architecture of Computing Systems, 2009
2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2008
EURASIP J. Embed. Syst., 2008
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Embed. Syst., 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
EURASIP J. Embed. Syst., 2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
A Code Compression Method with Confidentiality and Integrity Checking.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Tech. Sci. Informatiques, 2006
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Microprocess. Microsystems, 2006
Int. J. Embed. Syst., 2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Secure Architecture in Embedded Systems: an Overview.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006
2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
An estimation and exploration methodology from system-level specifications: application to FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Fast Design Space Exploration Method for Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2000
ACM Trans. Design Autom. Electr. Syst., 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1998
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
1997
ACM Trans. Design Autom. Electr. Syst., 1997
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
1996
Proceedings of the 9th International Symposium on System Synthesis, 1996