Andrew M. Fuller

According to our database, Andrew M. Fuller authored at least 3 papers between 2007 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.

Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen

IEEE J. Solid State Circuits, 2010

2007

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS.

John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz

IEEE J. Solid State Circuits, 2007

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications.

Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007