Nhat Nguyen

According to our database1, Nhat Nguyen authored at least 26 papers between 1999 and 2022.

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Bibliography

2022
Multi-Agent Data Collection in Non-Stationary Environments.
Proceedings of the 23rd IEEE International Symposium on a World of Wireless, 2022

Approach portfolio selection for Vietnamese stock market based on nonlinear shrinkage method.
Proceedings of the 14th International Conference on Knowledge and Systems Engineering, 2022

2021
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

Voting shrinkage algorithm for Covariance Matrix Estimation and its application to portfolio selection.
Proceedings of the 2020 RIVF International Conference on Computing and Communication Technologies, 2020

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

The Roads of Your Veins: Visualizing Map and Vein Data Matching.
Proceedings of the Extended Abstracts of the 2020 CHI Conference on Human Factors in Computing Systems, 2020

2019
DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling.
IEEE J. Solid State Circuits, 2019

2018
A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016
Dependable Traffic Control Strategies for Urban and Freeway Networks.
Mob. Networks Appl., 2016

2015
A Context-Aware Healthcare Architecture for the Elderly.
Proceedings of the Context-Aware Systems and Applications - 4th International Conference, 2015

2014
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits, 2014

An Adaptive Body-Biased Clock Generation System in 28nm CMOS.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Power-efficient I/O design considerations for high-bandwidth applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits, 2010

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Support-Graph Preconditioners.
SIAM J. Matrix Anal. Appl., 2006

Computational Science and Engineering Online (CSE-Online): A Cyber-Infrastructure for Scientific Computing.
J. Chem. Inf. Model., 2006

2001
Efficient generalized cross-validation with applications to parametric image restoration and resolution enhancement.
IEEE Trans. Image Process., 2001

A computationally efficient superresolution image reconstruction algorithm.
IEEE Trans. Image Process., 2001

2000
An Efficient Wavelet-Based Algorithm for Image Superresolution.
Proceedings of the 2000 International Conference on Image Processing, 2000

1999
Preconditioners for regularized image superresolution.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999


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