John M. Wilson

According to our database, John M. Wilson authored at least 27 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.

Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

IEEE J. Solid State Circuits, April, 2024

2023

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.

Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

IEEE J. Solid State Circuits, 2023

2022

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.

Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.

Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.

John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.

Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

Hardware-Enabled Artificial Intelligence.

William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.

John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.

Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module.

Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.

Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers.

Laura Fick, Dennis Sylvester, John W. Poulton, John M. Wilson, C. Thomas Gray

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.

John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.

John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray

IEEE J. Solid State Circuits, 2013

2011

Power-efficient I/O design considerations for high-bandwidth applications.

John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.

Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen

IEEE J. Solid State Circuits, 2010

Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications.

Paul D. Franzon, John M. Wilson, Ming Li

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling.

Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon

IEEE Trans. Very Large Scale Integr. Syst., 2009

2007

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.

Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver.

Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon

IEEE J. Solid State Circuits, 2006

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling.

Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver.

Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Demystifying 3D ICs: The Pros and Cons of Going Vertical.

W. Rhett Davis, John M. Wilson, Stephen E. Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael B. Steer, Paul D. Franzon

IEEE Des. Test Comput., 2005

Driver pre-emphasis techniques for on-chip global buses.

Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004

Simplified delay design guidelines for on-chip global interconnects.

Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2002

4 Gbps high-density AC coupled interconnection.

Stephen E. Mick, John M. Wilson, Paul D. Franzon

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1999

MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.

B. E. Duewer, John M. Wilson, D. A. Winick, Paul D. Franzon

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999