Yohan Frans
Orcid: 0000-0002-4336-9751
According to our database1,
Yohan Frans
authored at least 44 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
2021
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the European Conference on Optical Communications, 2020
2019
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 56 Gb/s 6 mW 300 um<sup>2</sup> inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
IEEE J. Solid State Circuits, 2016
A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2010
IEEE J. Solid State Circuits, 2010
2009
IEEE J. Solid State Circuits, 2009
2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006