Simon Li

Orcid: 0000-0002-7929-2442

According to our database1, Simon Li authored at least 33 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
A hybrid algorithm for task sequencing problems with iteration in product development.
J. Oper. Res. Soc., 2022

MULTI-AGENT SYSTEM MODEL FOR DYNAMIC SCHEDULING IN FLEXIBILE JOB SHOP SUBJECT TO RANDOM MACHINE BREAKDOWN.
Proceedings of the Winter Simulation Conference, 2022

2021
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021

Multi-Agent System Model for Dynamic Scheduling in Flexibile Job Shops.
Proceedings of the Winter Simulation Conference, 2021

2020

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Inferring the Optimal Policy using Markov Chain Monte Carlo.
CoRR, 2019

Bringing Open Data to Whole Slide Imaging.
Proceedings of the Digital Pathology - 15th European Congress, 2019

2018
Information-Theoretic Privacy for Smart Metering Systems with a Rechargeable Battery.
IEEE Trans. Inf. Theory, 2018

2016
Risk analysis for the supplier selection problem using failure modes and effects analysis (FMEA).
J. Intell. Manuf., 2016

Matrix-based hierarchical clustering for developing product architecture.
Concurr. Eng. Res. Appl., 2016

Matrix-based quality tools for concept generation in eco-design.
Concurr. Eng. Res. Appl., 2016

Privacy-optimal strategies for smart metering systems with a rechargeable battery.
Proceedings of the 2016 American Control Conference, 2016

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

Product customization of tablet computers based on the information of online reviews by customers.
J. Intell. Manuf., 2015

Structure of optimal privacy-preserving policies in smart-metered systems with a rechargeable battery.
Proceedings of the 16th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2015


2014
Identification of Clusters and Interfaces for Supporting the Implementation of Change Requests.
IEEE Trans. Engineering Management, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
A matrix-based modularization approach for supporting secure collaboration in parametric design.
Comput. Ind., 2012

2011
Automated segmentation and alignment of mitotic nuclei for kymograph visualisation.
Proceedings of the 8th IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2011

2010
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits, 2010

Lagrangian Relaxation Approach for Decentralized Decision Making in Engineering Design.
J. Comput. Inf. Sci. Eng., 2010

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2008
Needs-Centric Searching and Ranking Based on Customer Reviews.
Proceedings of the 10th IEEE International Conference on E-Commerce Technology (CEC 2008) / 5th IEEE International Conference on Enterprise Computing, 2008

Computer-aided interpretation of ICU portable chest images: automated detection of endotracheal tubes.
Proceedings of the Medical Imaging 2008: Computer-Aided Diagnosis, 2008

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.
IEEE J. Solid State Circuits, 2003

2002
A computerized team approach for concurrent product and process design optimization.
Comput. Aided Des., 2002

2000
Modeling Concurrent Product Design: A Multifunctional Team Approach.
Concurr. Eng. Res. Appl., 2000

1995
Microarchitecture of HaL's CPU.
Proceedings of the COMPCON '95: Technologies for the Information Superhighway, 1995


  Loading...