Andrew R. Pleszkun

According to our database1, Andrew R. Pleszkun authored at least 25 papers between 1982 and 2003.

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Bibliography

2003
A Performance Analysis of the iSCSI Protocol.
Proceedings of the 20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies, 2003

1998
Implementation of Precise Interupts in Pipelined Processors.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Confidence Estimation for Speculation Control.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997
Managing data caches using selective cache line replacement.
Int. J. Parallel Program., 1997

1995
A modified approach to data cache management.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994
Techniques for compressing program address traces.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1992
MISC: a Multiple Instruction Stream Computer.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991
Implementation of the PIPE Processor.
Computer, 1991

Strategies for Achieving Improved Processor Throughput.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1990
An evaluation of functional unit lengths for single-chip processors.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989
Improving Performance of Small On-Chip Instruction Caches.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1988
Implementing Precise Interrupts in Pipelined Processors.
IEEE Trans. Computers, 1988

Multiple instruction issue and single-chip processors.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

The Performance Potential of Multiple Functional Unit Processors.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1987
On the Structural Locality of Reference in LISP List Access Streams.
Inf. Process. Lett., 1987

The Architecture of Lisp Machines.
Computer, 1987

WISQ: A Restartable Architecture Using Queues.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1986
An Architecture for Efficient Lisp List Access.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Features of the Structured Memory Access (SMA) Architecture.
Proceedings of the Spring COMPCON'86, 1986

1985
Implementation of Precise Interrupts in Pipelined Processors.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

PIPE: A VLSI Decoupled Architecture.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

An algorithm for design rule checking on a multiprocessor.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1983
Structured Memory Access Architecture.
Proceedings of the International Conference on Parallel Processing, 1983

1982
A Structured Memory Access Architecture
PhD thesis, 1982


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