Srilatha Manne

Orcid: 0009-0005-6153-8255

According to our database1, Srilatha Manne authored at least 32 papers between 1995 and 2023.

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Bibliography

2023
Design Space Exploration and Optimization for Carbon-Efficient Extended Reality Systems.
CoRR, 2023


Carbon-Efficient Design Optimization for Computing Systems.
Proceedings of the 2nd Workshop on Sustainable Computer Systems, 2023

2022
AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Socio-Technological Challenges and Opportunities: Paths Forward.
CoRR, 2021

2020
A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing.
CoRR, 2020

2017
If You Build It, Will They Come?
IEEE Micro, 2017

Workload characterization of interactive cloud services on big and small server platforms.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

2016
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.
CoRR, 2016

Quantifying Energy Use in Dense Shared Memory HPC Node.
Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, 2016

2015
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Coordinated energy management in heterogeneous processors.
Sci. Program., 2014

A comparison of core power gating strategies implemented in modern hardware.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

2013
Automating Stressmark Generation for Testing Processor Voltage Fluctuations.
IEEE Micro, 2013

Cooperative boosting: needy versus greedy power management.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Performance boosting under reliability and power constraints.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
AUDIT: Stress Testing the Automatic Way.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Something old and something new: P-states can borrow microarchitecture techniques too.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2008
Accelerating two-dimensional page walks for virtualized systems.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
Perturbation-based Fault Screening.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2002
Asim: A Performance Model Framework.
Computer, 2002

Loose Loops Sink Chips.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
Selective Branch Inversion: Confidence Estimation for Branch Predictors.
Int. J. Parallel Program., 2001

Power and energy reduction via pipeline balancing.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

1999
Branch Prediction Using Selective Branch Inversion.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
Power and performance tradeoffs using various caching strategies.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Pipeline Gating: Speculation Control for Energy Reduction.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Confidence Estimation for Speculation Control.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997
Remembrance of Things Past: Locality and Memory in BDDs.
Proceedings of the 34st Conference on Design Automation, 1997

1996
New Algorithms for Gate Sizing: A Comparative Study.
Proceedings of the 33st Conference on Design Automation, 1996

1995
CMOS dynamic power estimation based on collapsible current source transistor modeling.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Computing the Maximum Power Cycles of a Sequential Circuit.
Proceedings of the 32st Conference on Design Automation, 1995


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