Matthew K. Farrens

According to our database1, Matthew K. Farrens
  • authored at least 53 papers between 1989 and 2017.
  • has a "Dijkstra number"2 of three.

Timeline

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Bibliography

2017
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Improving network performance on multicore systems: Impact of core affinities on high throughput flows.
Future Generation Comp. Syst., 2016

2015
Performance Analysis of Real-Time Covert Timing Channel Detection Using a Parallel System.
Proceedings of the Network and System Security - 9th International Conference, 2015

2014
Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches.
IEEE/ACM Trans. Netw., 2014

PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks.
IEEE Trans. Computers, 2014

Analysis of the effect of core affinity on high-throughput flows.
Proceedings of the Fourth International Workshop on Network-Aware Data Management, 2014

Impact of the end-system and affinities on the throughput of high-speed flows.
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014

2013
Photonic Interconnects: A Computer Architect's Perspective
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 9781627052122, 2013

Characterizing the impact of end-system affinities on the end-to-end performance of high-speed flows.
Proceedings of the Third International Workshop on Network-Aware Data Management, 2013

2012
DCOF - An Arbitration Free Directly Connected Optical Fabric.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Minimizing the Data Transfer Time Using Multicore End-System Aware Flow Bifurcation.
Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012

Cache-aware affinitization on commodity multicores for high-speed network flows.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011
Inferring packet dependencies to improve trace based simulation of on-chip networks.
Proceedings of the NOCS 2011, 2011

Resilient microring resonator based photonic networks.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Introspective end-system modeling to optimize the transfer time of rate based protocols.
Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, 2011

Addressing system-level trimming issues in on-chip nanophotonic networks.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Performance Evaluation of a Multicore System with Optically Connected Memory Modules.
Proceedings of the NOCS 2010, 2010

2008
Techniques for increasing effective data bandwidth.
Proceedings of the 26th International Conference on Computer Design, 2008

Design and evaluation of an optical CPU-DRAM interconnect.
Proceedings of the 26th International Conference on Computer Design, 2008

Packet prediction for speculative cut-through switching.
Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008

2002
Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.
J. Instruction-Level Parallelism, 2002

2001
Improving Bandwidth Utilization using Eager Writeback.
J. Instruction-Level Parallelism, 2001

2000
Eager writeback - a technique for improving bandwidth utilization.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

HLS: combining statistical and symbolic simulation to guide microprocessor designs.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Branch Transition Rate: A New Metric for Improved Branch Classification Analysis.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Code Partitioning in Decoupled Compilers.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

The Decoupled-Style Prefetch Architecture (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Exploiting ILP in Page-based Intelligent Memory.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1998
The architecture curriculum at UC-Davis.
Proceedings of the 1998 workshop on Computer architecture education, 1998

Utilizing Reuse Information in Data Cache Management.
Proceedings of the 12th international conference on Supercomputing, 1998

1997
Managing data caches using selective cache line replacement.
International Journal of Parallel Programming, 1997

1996
Evaluating the Effects of Predicated Execution on Branch Prediction.
International Journal of Parallel Programming, 1996

Guest Editors' Introduction.
International Journal of Parallel Programming, 1996

Distributed Decentralized Computing.
ACM Comput. Surv., 1996

1995
A modified approach to data cache management.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994
Code scheduling for multiple instruction stream architectures.
International Journal of Parallel Programming, 1994

A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Techniques for extracting instruction level parallelism on MIMD architectures.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A comparision of superscalar and decoupled access/execute architectures.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992
MISC: a Multiple Instruction Stream Computer.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Modifying VM hardware to reduce address pin requirements.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

A partitioned translation lookaside buffer approach to reducing address bandwith.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension.
Proceedings of the 6th International Parallel Processing Symposium, 1992

1991
Implementation of the PIPE Processor.
IEEE Computer, 1991

Alleviation of tree saturation in multistage interconnection networks.
Proceedings of the Proceedings Supercomputing '91, 1991

Workload and Implementation Considerations for Dynamic Base Register Caching.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

An Analysis of the Information Content of Address Reference Streams.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Strategies for Achieving Improved Processor Throughput.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Dynamic Base Register Caching: A Technique for Reducing Address Bus Width.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1990
Address compression through base register caching.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

An evaluation of functional unit lengths for single-chip processors.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989
Improving Performance of Small On-Chip Instruction Caches.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989


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