Matthew K. Farrens

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01774-2, 2013

Characterizing the impact of end-system affinities on the end-to-end performance of high-speed flows.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Network-Aware Data Management, 2013

2012

DCOF - An Arbitration Free Directly Connected Optical Fabric.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Minimizing the Data Transfer Time Using Multicore End-System Aware Flow Bifurcation.

[BibT_eX]

[DOI]

Vishal Ahuja

Dipak Ghosal

Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012

Cache-aware affinitization on commodity multicores for high-speed network flows.

[BibT_eX]

[DOI]

Vishal Ahuja

Dipak Ghosal

Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011

Inferring packet dependencies to improve trace based simulation of on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Resilient microring resonator based photonic networks.

[BibT_eX]

[DOI]

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Introspective end-system modeling to optimize the transfer time of rate based protocols.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, 2011

Addressing system-level trimming issues in on-chip nanophotonic networks.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010

Performance Evaluation of a Multicore System with Optically Connected Memory Modules.

[BibT_eX]

[DOI]

Paul Vincent Mejia

Rajeevan Amirtharajah

Proceedings of the NOCS 2010, 2010

2008

Techniques for increasing effective data bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Design and evaluation of an optical CPU-DRAM interconnect.

[BibT_eX]

[DOI]

Amit Hadke

Tony Benavides

Rajeevan Amirtharajah

Proceedings of the 26th International Conference on Computer Design, 2008

Packet prediction for speculative cut-through switching.

[BibT_eX]

[DOI]

Paul Congdon

Prasant Mohapatra

Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008

2002

Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.

[BibT_eX]

[DOI]

Mark Oskin

Frederic T. Chong

J. Instr. Level Parallelism, 2002

2001

Improving Bandwidth Utilization using Eager Writeback.

[BibT_eX]

[DOI]

Hsien-Hsin S. Lee

J. Instr. Level Parallelism, 2001

2000

Eager writeback - a technique for improving bandwidth utilization.

[BibT_eX]

[DOI]

Hsien-Hsin S. Lee

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

HLS: combining statistical and symbolic simulation to guide microprocessor designs.

[BibT_eX]

[DOI]

Mark Oskin

Frederic T. Chong

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Branch Transition Rate: A New Metric for Improved Branch Classification Analysis.

[BibT_eX]

[DOI]

Michael Haungs

Phil Sallee

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Code Partitioning in Decoupled Compilers.

[BibT_eX]

[DOI]

Kevin D. Rich

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

The Decoupled-Style Prefetch Architecture (Research Note).

[BibT_eX]

[DOI]

Kevin D. Rich

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999

Exploiting ILP in Page-based Intelligent Memory.

[BibT_eX]

[DOI]

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1998

The architecture curriculum at UC-Davis.

[BibT_eX]

[DOI]

Proceedings of the 1998 workshop on Computer architecture education, 1998

Utilizing Reuse Information in Data Cache Management.

[BibT_eX]

[DOI]

Proceedings of the 12th international conference on Supercomputing, 1998

1997

Managing data caches using selective cache line replacement.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1997

1996

Evaluating the Effects of Predicated Execution on Branch Prediction.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1996

Guest Editors' Introduction.

[BibT_eX]

Wen-mei W. Hwu

Int. J. Parallel Program., 1996

Distributed Decentralized Computing.

[BibT_eX]

[DOI]

ACM Comput. Surv., 1996

1995

A modified approach to data cache management.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994

Code scheduling for multiple instruction stream architectures.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1994

A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993

Techniques for extracting instruction level parallelism on MIMD architectures.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A comparision of superscalar and decoupled access/execute architectures.

[BibT_eX]

[DOI]

Pius Ng

Phil Nico

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

MISC: a Multiple Instruction Stream Computer.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Modifying VM hardware to reduce address pin requirements.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

A partitioned translation lookaside buffer approach to reducing address bandwith.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension.

[BibT_eX]

[DOI]

Allison Woodruff

Proceedings of the 6th International Parallel Processing Symposium, 1992

1991

Implementation of the PIPE Processor.

[BibT_eX]

[DOI]

Computer, 1991

Alleviation of tree saturation in multistage interconnection networks.

[BibT_eX]

[DOI]

Brad Wetmore

Allison Woodruff

Proceedings of the Proceedings Supercomputing '91, 1991

Workload and Implementation Considerations for Dynamic Base Register Caching.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

An Analysis of the Information Content of Address Reference Streams.

[BibT_eX]

[DOI]

Jeffrey C. Becker

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Strategies for Achieving Improved Processor Throughput.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Dynamic Base Register Caching: A Technique for Reducing Address Bus Width.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1990

Address compression through base register caching.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

An evaluation of functional unit lengths for single-chip processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989

Improving Performance of Small On-Chip Instruction Caches.

[BibT_eX]

[DOI]