Gurindar S. Sohi

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997

Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.

[BibT_eX]

[DOI]

Andreas Moshovos

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Dynamic Instruction Reuse.

[BibT_eX]

[DOI]

Avinash Sodani

Proceedings of the 24th International Symposium on Computer Architecture, 1997

Dynamic Speculation and Synchronization of Data Dependences.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Computer Architecture, 1997

Memory Systems.

[BibT_eX]

Doug Burger

James R. Goodman

Proceedings of the Computer Science and Engineering Handbook, 1997

1996

ARB: A Hardware Mechanism for Dynamic Reordering of Memory References.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

High-Bandwidth Address Translation for Multiple-Issue Processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995

The microarchitecture of superscalar processors.

[BibT_eX]

[DOI]

James E. Smith

Proc. IEEE, 1995

Zero-cycle loads: microarchitecture support for reducing load latency.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Multiscalar Processors.

[BibT_eX]

[DOI]

Scott E. Breach

T. N. Vijaykumar

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Streamlining Data Cache Access with Fast Address Calculation.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1994

Request Combining in Multiprocessors with Arbitrary Interconnection Networks.

[BibT_eX]

[DOI]

Alvin R. Lebeck

IEEE Trans. Parallel Distributed Syst., 1994

Efficient Detection of All Pointer and Array Access Errors.

[BibT_eX]

[DOI]

Scott E. Breach

Proceedings of the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation (PLDI), 1994

The anatomy of the register file in a multiscalar processor.

[BibT_eX]

[DOI]

Scott E. Breach

T. N. Vijaykumar

Dionisios N. Pnevmatikatos

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Guarded Executing and Branch Prediction in Dynamic ILP Processors.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993

High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

IEEE Trans. Computers, 1993

Control flow prediction for dynamic ILP processors.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment.

[BibT_eX]

[DOI]

MenChow Chiang

IEEE Trans. Computers, 1992

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

Dynamic Dependency Analysis of Ordinary Programs.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors.

[BibT_eX]

[DOI]

MenChow Chiang

Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1991

An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks.

[BibT_eX]

[DOI]

Wei-Chung Hsu

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

High-Bandwidth Data Memory Systems for Superscalar Processors.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-IV Proceedings, 1991

1990

The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control.

[BibT_eX]

[DOI]

Steven L. Scott

IEEE Trans. Parallel Distributed Syst., 1990

The use of intermediate memories for low-latency memory access in supercomputer scalar units.

[BibT_eX]

[DOI]

Wei-Chung Hsu

J. Supercomput., 1990

Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

Design and Analysis of a Gracefully Degrading Interleaved Memory System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

Scalable Shared-Memory Multiprocessor Architectures.

[BibT_eX]

[DOI]

Computer, 1990

Exploitation of operation-level parallelism in a processor of the CRAY X-MP.

[BibT_eX]

[DOI]

Wei-Chung Hsu

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1989

Performance Analysis of Hierarchical Cache-Consistent Multiprocessors.

[BibT_eX]

[DOI]

Mary K. Vernon

Rajeev Jog

Perform. Evaluation, 1989

On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns.

[BibT_eX]

V. S. Madan

C.-J. Peng

Proceedings of the Logic Programming, 1989

Using Feedback to Control Tree Saturation in Multistage Interconnection Networks.

[BibT_eX]

[DOI]

Steven L. Scott

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Restricted Fetch&Phi operations for parallel processing.

[BibT_eX]

[DOI]

James E. Smith

James R. Goodman

Proceedings of the 3rd international conference on Supercomputing, 1989

A study of time-redundant fault tolerance techniques for high-performance pipelined computers.

[BibT_eX]

[DOI]

Kewal K. Saluja

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

Tradeoffs in Instruction Format Design for Horizontal Architectures.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-III Proceedings, 1989

1988

Multiple instruction issue and single-chip processors.

[BibT_eX]

[DOI]

Andrew R. Pleszkun

Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

The Performance Potential of Multiple Functional Unit Processors.

[BibT_eX]

[DOI]

Andrew R. Pleszkun

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1987

Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1986

Features of the Structured Memory Access (SMA) Architecture.

[BibT_eX]

Proceedings of the Spring COMPCON'86, 1986

1985

Blast: A Machine Architecture for High-Speed List Processing Using Associative Tables (Traversal, Pointers)

[BibT_eX]

[DOI]

PhD thesis, 1985

An Efficient LISP-Execution Architecture with a New Representation for List Structures.

[BibT_eX]

[DOI]