Anton Blad

According to our database1, Anton Blad authored at least 13 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2012
Spectrum sensing of OFDM signals in the presence of CFO: New algorithms and empirical evaluation using USRP.
Proceedings of the 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2012

Cooperative communications with HARQ in a wireless mesh network based on 3GPP LTE.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures.
PhD thesis, 2011

FPGA implementation of rate-compatible QC-LDPC code decoder.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures.
Circuits Syst. Signal Process., 2010

Power Efficient Partial Repeated Cooperation Scheme with Regular LDPC Code.
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


2008
Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators.
EURASIP J. Adv. Signal Process., 2008

Bit-level optimized FIR filter architectures for high-speed decimation applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006
Design trade-offs for linear-phase FIR decimation filters and ΣΔ-modulators.
Proceedings of the 14th European Signal Processing Conference, 2006

A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
An early decision decoding algorithm for LDPC codes using dynamic thresholds.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005


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