Tom Vander Aa

According to our database1, Tom Vander Aa authored at least 43 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A high-level library for multidimensional arrays programming in computational science.
Concurrency and Computation: Practice and Experience, 2018

Enhancing Machine Learning Optimization Algorithms by Leveraging Memory Caching (Research Poster).
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

HyperLoom: A Platform for Defining and Executing Scientific Pipelines in Distributed Environments.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

Cache-efficient Gradient Descent Algorithm.
Proceedings of the 26th European Symposium on Artificial Neural Networks, 2018

2017
Distributed Matrix Factorization using Asynchrounous Communication.
CoRR, 2017

Distributed Bayesian Probabilistic Matrix Factorization.
CoRR, 2017

Distributed Bayesian Probabilistic Matrix Factorization.
Proceedings of the International Conference on Computational Science, 2017

2016
Exploring Parallel Implementations of the Bayesian Probabilistic Matrix Factorization.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Exploring a Distributed Iterative Reconstructor Based on Split Bregman Using PETSc.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

Distributed Bayesian Probabilistic Matrix Factorization.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

2015
Array Interleaving - An Energy-Efficient Data Layout Transformation.
ACM Trans. Design Autom. Electr. Syst., 2015

ExaShark: a scalable hybrid array kit for exascale simulation.
Proceedings of the Symposium on High Performance Computing, 2015

2014
Hard versus Soft Software Defined Radio.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

2013
Data memory optimization in LTE downlink.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Power Estimation at Different Abstraction Levels for Wireless Baseband Processors.
J. Low Power Electronics, 2012

Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors.
IEEE Micro, 2011

High level analysis of trade-offs across different partitioning schemes for wireless applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A multi-threaded coarse-grained array processor for wireless baseband.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2010
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.
Signal Processing Systems, 2010

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Signal Processing Systems, 2010

SDR platform for 802.11n and 3-GPP LTE.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010


Compilation techniques for CGRAs: exploring all parallelization approaches.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2008
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.
Signal Processing Systems, 2008

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Instruction Transfer And Storage Exploration for Low Energy VLIWs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Hardware and a Tool Chain for ADRES.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
IEEE Trans. Computers, 2005

Instruction buffering exploration for low energy embedded processors.
J. Embedded Computing, 2005

Combining Data and Instruction Memory Energy Optimizations for Embedded Applications.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
L0 buffer energy optimization through scheduling and exploration.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

L0 Cluster Synthesis and Operation Shuffling.
Proceedings of the Integrated Circuit and System Design, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Instruction Buffering Exploration for Low Energy Embedded Processors.
Proceedings of the Integrated Circuit and System Design, 2003

Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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